Commit Graph

174 Commits

Author SHA1 Message Date
Andre Richter
c6e12f7bcf
Fix wrong serial selection in qemu. Simplify code. 2019-02-03 21:48:55 +01:00
Andre Richter
c21c46b362
Don't use super 2019-02-03 21:44:00 +01:00
Andre Richter
14022d69c3
Align code with updates that went into follow-up tutorials 2019-02-03 21:39:26 +01:00
Andre Richter
2905ae0b09
Add README for 0B_exception_levels 2019-02-02 21:43:10 +01:00
Andre Richter
56eee2a097
Update README.md 2019-02-02 20:15:12 +01:00
Andre Richter
b5b065b3c2
Add placeholder for upcoming lessons. 2019-02-01 19:34:25 +01:00
Andre Richter
8f15a559c5
Remove old exceptions lesson 2019-02-01 19:28:09 +01:00
Andre Richter
d294809901
Rebase Exceptions Groundwork lesson 2019-02-01 19:28:09 +01:00
Andre Richter
48cf71b6d4
Add code for 0F_DMA_memory 2019-02-01 19:28:09 +01:00
Andre Richter
c6e6ccd2a4
Add code for global println lesson 2019-02-01 19:28:09 +01:00
Andre Richter
4f4e88cfbe
Update binaries generated by newer rustc 2019-02-01 19:28:09 +01:00
Andre Richter
2a4fdc4ece
Add missing comment that triggered build errors in new nightly rust.
Also, update binaries generated by new nightly version:
rustc 1.33.0-nightly (75a369c5b 2019-01-12)
2019-01-13 14:16:59 +01:00
Andre Richter
e77745e545
Fix correct term usec for microseconds 2019-01-12 22:12:04 +01:00
Andre Richter
052f3e9d9c
Add a pre-commit hook 2019-01-12 21:55:28 +01:00
Andre Richter
b4ce7d7e1d
Correct some Copyright years 2019-01-12 21:55:28 +01:00
Andre Richter
ecafec1d05
Add copyright year checks. Ran Rubocop as well. 2019-01-12 21:55:18 +01:00
Andre Richter
0d25085af7
Fix clippy warning 2019-01-05 20:18:59 +01:00
Andre Richter
1b69b5dcc2
Make sure Pagetable arrays are 4 KiB aligned 2019-01-05 20:17:31 +01:00
Andre Richter
aa8ec19e8b
Add publicly available docs 2019-01-05 20:01:24 +01:00
Andre Richter
40c5760260
Remove not needed features 2019-01-05 20:00:26 +01:00
Andre Richter
5db5147a1d
forgot an unsafe 2019-01-01 21:09:41 +01:00
Andre Richter
4ecddb20de
Add tutorial 0E - Exceptions: Groundwork 2019-01-01 16:54:22 +01:00
Andre Richter
90d88f65b6
Streamlining, cleanup, and minor fixes. 2018-12-31 01:19:57 +01:00
Andre Richter
c017fc16dd
Minor Cargo.lock fix 2018-12-31 01:19:02 +01:00
Andre Richter
0824b0ecaa
Rework utils 2018-12-31 01:18:54 +01:00
Andre Richter
0802adca1c
Fix accidental local path in dependency 2018-12-22 21:09:15 +01:00
Andre Richter
52e0f4c850
mmu: Add more descriptive comments 2018-12-22 20:58:41 +01:00
Andre Richter
7f8960bb81
09_delays: Fix delays in main 2018-12-22 20:58:41 +01:00
Andre Richter
ad2d0d1182
🎉 Update to Rust 2018 🎉 2018-12-22 20:56:09 +01:00
Albert Cervin
977343de2e Fix a small error in the RO mapping (#9)
The error would cause one page too much to be marked as read only.
Instead, calculate the appropriate page table indices for the read-only
region together with a comment explaining the subtraction by one.
2018-12-22 20:37:18 +01:00
Tyler Christensen
d981f670b1 Fix two timing issues in delays.rs (#8)
* Fix two timing issues in delays.rs

These changes correct the implementations of delays::SysTmr::wait_msec_st
and delays::wait_msec to behave correctly and consistently with one another.

* Port delay fix from 09_delays to 0B_exception_levels

I believe this covers all copies of this bug in the codebase.

* Rebuild tutorial kernels with delay fixes
2018-12-01 12:35:21 +01:00
Andre Richter
83fdecc647
Add simple soft-panic test 2018-11-01 22:44:44 +01:00
Andre Richter
3e10cd52a1
Add nm target 2018-11-01 22:44:16 +01:00
Andre Richter
c004e78e90
Safe implementations of uart::dec() and divisions
The previous implementation of uart::dec() forced the compiler to emit a
software out-of-bounds acces check into the code, bloating it a bit. Prevent
that by using an iterator instead.

Same is true for the ordinary division operator that was used in multiple places
in the benchmark code. Here, the compiler emitted software-checks for divison by
zero. Prevent this by using `checked_div()` where we can implement our own
"panic" handling.
2018-11-01 22:07:46 +01:00
Andre Richter
17b582f774
Update README.md 2018-10-29 22:53:54 +01:00
Andre Richter
c62b79f09b
UART1 output on QEMU. Rework some Readmes. 2018-10-29 22:52:58 +01:00
Andre Richter
b6fafa6191
Use SP_EL1 as EL1 stack instead of SP_EL0 2018-10-27 20:26:47 +02:00
Andre Richter
b1786d5110
Update README.md 2018-10-24 09:06:30 +02:00
Andre Richter
5a7f77eae8
Update README.md 2018-10-24 09:05:33 +02:00
Andre Richter
937397d6b2
Update README.md 2018-10-22 21:59:27 +02:00
Andre Richter
6b4bd0e881
Formatting didn't work. Try again. 2018-10-21 20:20:39 +02:00
Andre Richter
d488436f04
Add myself to License file; Reformat 2018-10-21 20:18:51 +02:00
Andre Richter
f5d97b5723
Restructure Readme
Also, closes #5
2018-10-21 20:16:27 +02:00
Andre Richter
a44d487d89
Update .travis.yml 2018-10-16 22:22:13 +02:00
Andre Richter
fb17d56991
Adapter Travis badge to moved repo 2018-10-13 21:32:06 +02:00
Andre Richter
2046da5eab
Add objdump target 2018-10-03 00:02:45 +02:00
Andre Richter
3f92aab6e7
Bump extern crates
cortex-a -> 2.2.1
panic-abort -> 0.3.1
2018-10-02 23:47:09 +02:00
Andre Richter
6d135ee441
Makefile: Don't delete kernel8 2018-10-02 23:34:01 +02:00
Andre Richter
37fe055082
Alignment. Binaries from newer Rust version. 2018-10-02 23:16:04 +02:00
Andre Richter
68de789d15
0D: Instruction caching and better benchmark function.
The previous benchmark function had a few flaws. First of all, it wasn't
idiomatic Rust, because we used a loop construct that you would expect in C.
Revamped that by using an iterator. Also, the previous benchmark got heavily
optimized by the compiler, which unrolled the inner loop it into a huge sequence
of consecutive loads and stores, resulting in lots of instructions that needed
to be fetched from DRAM. Additionally, instruction caching was not turned on.

The new code compiles into two tight loops, fully leveraging the power of the I
and D caches, and providing an great showcase.
2018-10-02 22:59:27 +02:00