Fix two timing issues in delays.rs (#8)

* Fix two timing issues in delays.rs

These changes correct the implementations of delays::SysTmr::wait_msec_st
and delays::wait_msec to behave correctly and consistently with one another.

* Port delay fix from 09_delays to 0B_exception_levels

I believe this covers all copies of this bug in the codebase.

* Rebuild tutorial kernels with delay fixes

09_delays/src/delays.rs

@@ -89,7 +89,7 @@ impl SysTmr {
         // mean infinite loop
         if t > 0 {
             loop {
-                if self.get_system_timer() < (t + n) {
+                if self.get_system_timer() > (t + n) {
                     break;
                 }
             }
@@ -108,7 +108,7 @@ pub fn wait_msec(n: u32) {
     let frq = CNTFRQ_EL0.get();
 
     // Calculate number of ticks
-    let tval = (frq as u32 / 1000) * n;
+    let tval = (u64::from(frq) * u64::from(n) / 1_000_000) as u32;
 
     // Set the compare value register
     CNTP_TVAL_EL0.set(tval);

0B_exception_levels/src/delays.rs

@@ -35,7 +35,7 @@ pub fn wait_msec(n: u32) {
     let frq = CNTFRQ_EL0.get();
 
     // Calculate number of ticks
-    let tval = (frq as u32 / 1000) * n;
+    let tval = (u64::from(frq) * u64::from(n) / 1_000_000) as u32;
 
     // Set the compare value register
     CNTP_TVAL_EL0.set(tval);