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@ -397,9 +397,9 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/exception.rs 14_
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+ memory::Address,
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+};
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use core::{cell::UnsafeCell, fmt};
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use cortex_a::{barrier, regs::*};
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use register::InMemoryRegister;
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@@ -50,6 +54,20 @@
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use cortex_a::{asm::barrier, registers::*};
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use tock_registers::{
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@@ -53,6 +57,20 @@
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// Private Code
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//--------------------------------------------------------------------------------------------------
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@ -420,7 +420,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/exception.rs 14_
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/// Prints verbose information about the exception and then panics.
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fn default_exception_handler(e: &ExceptionContext) {
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panic!(
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@@ -166,7 +184,9 @@
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@@ -169,7 +187,9 @@
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writeln!(f, " - {}", ec_translation)?;
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// Raw print of instruction specific syndrome.
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@ -451,7 +451,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu/trans
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},
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};
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use core::convert;
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@@ -117,12 +120,9 @@
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@@ -121,12 +124,9 @@
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}
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trait StartAddr {
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@ -465,7 +465,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu/trans
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//--------------------------------------------------------------------------------------------------
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// Public Definitions
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//--------------------------------------------------------------------------------------------------
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@@ -137,10 +137,13 @@
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@@ -141,10 +141,13 @@
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/// Table descriptors, covering 512 MiB windows.
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lvl2: [TableDescriptor; NUM_TABLES],
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@ -482,7 +482,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu/trans
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//--------------------------------------------------------------------------------------------------
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// Private Code
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@@ -148,12 +151,8 @@
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@@ -152,12 +155,8 @@
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// The binary is still identity mapped, so we don't need to convert here.
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impl<T, const N: usize> StartAddr for [T; N] {
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@ -497,7 +497,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu/trans
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}
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}
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@@ -166,10 +165,10 @@
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@@ -170,10 +169,10 @@
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}
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/// Create an instance pointing to the supplied address.
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@ -510,7 +510,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu/trans
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val.write(
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STAGE1_TABLE_DESCRIPTOR::NEXT_LEVEL_TABLE_ADDR_64KiB.val(shifted as u64)
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+ STAGE1_TABLE_DESCRIPTOR::TYPE::Table
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@@ -226,7 +225,10 @@
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@@ -230,7 +229,10 @@
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}
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/// Create an instance.
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@ -522,7 +522,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu/trans
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let val = InMemoryRegister::<u64, STAGE1_PAGE_DESCRIPTOR::Register>::new(0);
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let shifted = phys_output_addr as u64 >> Granule64KiB::SHIFT;
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@@ -240,50 +242,193 @@
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@@ -244,50 +246,193 @@
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Self { value: val.get() }
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}
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@ -687,7 +687,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu/trans
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+ return Err("Virtual page is already mapped");
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}
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+
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+ *page_descriptor = PageDescriptor::from_output_addr(phys_page.as_ptr(), &attr);
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+ *page_descriptor = PageDescriptor::from_output_addr(phys_page.as_ptr(), attr);
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}
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Ok(())
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@ -733,7 +733,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu/trans
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}
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}
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@@ -292,6 +437,9 @@
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@@ -296,6 +441,9 @@
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//--------------------------------------------------------------------------------------------------
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#[cfg(test)]
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@ -755,8 +755,8 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu.rs 14
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+ memory::{mmu::TranslationGranule, Address, Physical},
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};
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use core::intrinsics::unlikely;
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use cortex_a::{barrier, regs::*};
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@@ -45,13 +45,6 @@
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use cortex_a::{asm::barrier, registers::*};
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@@ -46,13 +46,6 @@
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// Global instances
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//--------------------------------------------------------------------------------------------------
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@ -770,7 +770,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu.rs 14
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static MMU: MemoryManagementUnit = MemoryManagementUnit;
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//--------------------------------------------------------------------------------------------------
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@@ -86,7 +79,7 @@
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@@ -87,7 +80,7 @@
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/// Configure various settings of stage 1 of the EL1 translation regime.
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fn configure_translation_control(&self) {
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@ -779,7 +779,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu.rs 14
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TCR_EL1.write(
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TCR_EL1::TBI0::Used
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@@ -118,7 +111,10 @@
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@@ -119,7 +112,10 @@
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use memory::mmu::MMUEnableError;
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impl memory::mmu::interface::MMU for MemoryManagementUnit {
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@ -791,7 +791,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu.rs 14
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if unlikely(self.is_enabled()) {
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return Err(MMUEnableError::AlreadyEnabled);
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}
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@@ -133,13 +129,8 @@
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@@ -134,13 +130,8 @@
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// Prepare the memory attribute indirection register.
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self.set_up_mair();
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@ -806,7 +806,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu.rs 14
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self.configure_translation_control();
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@@ -162,33 +153,3 @@
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@@ -163,33 +154,3 @@
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SCTLR_EL1.matches_all(SCTLR_EL1::M::Enable)
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}
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}
|
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|
@ -852,10 +852,10 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi
|
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|
+use crate::{
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+ bsp::device_driver::common::MMIODerefWrapper, exception, synchronization::InitStateLock,
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+};
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use register::{mmio::*, register_bitfields, register_structs};
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|
//--------------------------------------------------------------------------------------------------
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@@ -56,12 +58,13 @@
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|
use tock_registers::{
|
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|
interfaces::{Readable, Writeable},
|
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|
|
register_bitfields, register_structs,
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@@ -60,12 +62,13 @@
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|
/// Representation of the GIC CPU interface.
|
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|
|
pub struct GICC {
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|
@ -870,7 +870,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi
|
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|
|
impl GICC {
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|
|
/// Create an instance.
|
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|
@@ -71,10 +74,15 @@
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@@ -75,10 +78,15 @@
|
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|
|
/// - The user must ensure to provide a correct MMIO start address.
|
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|
|
pub const unsafe fn new(mmio_start_addr: usize) -> Self {
|
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|
|
Self {
|
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|
|
@ -887,7 +887,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi
|
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|
|
/// Accept interrupts of any priority.
|
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|
|
///
|
|
|
|
|
/// Quoting the GICv2 Architecture Specification:
|
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|
|
@@ -87,7 +95,9 @@
|
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|
|
@@ -91,7 +99,9 @@
|
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|
|
/// - GICC MMIO registers are banked per CPU core. It is therefore safe to have `&self` instead
|
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|
|
|
/// of `&mut self`.
|
|
|
|
|
pub fn priority_accept_all(&self) {
|
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|
|
@ -898,7 +898,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi
|
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|
|
}
|
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|
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|
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|
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|
|
/// Enable the interface - start accepting IRQs.
|
|
|
|
|
@@ -97,7 +107,9 @@
|
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|
|
@@ -101,7 +111,9 @@
|
|
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|
|
/// - GICC MMIO registers are banked per CPU core. It is therefore safe to have `&self` instead
|
|
|
|
|
/// of `&mut self`.
|
|
|
|
|
pub fn enable(&self) {
|
|
|
|
@ -909,7 +909,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi
|
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|
|
}
|
|
|
|
|
|
|
|
|
|
/// Extract the number of the highest-priority pending IRQ.
|
|
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|
|
@@ -113,7 +125,8 @@
|
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|
|
@@ -117,7 +129,8 @@
|
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|
|
&self,
|
|
|
|
|
_ic: &exception::asynchronous::IRQContext<'irq_context>,
|
|
|
|
|
) -> usize {
|
|
|
|
@ -919,7 +919,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/// Complete handling of the currently active IRQ.
|
|
|
|
|
@@ -132,6 +145,8 @@
|
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|
|
@@ -136,6 +149,8 @@
|
|
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|
|
irq_number: u32,
|
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|
|
|
_ic: &exception::asynchronous::IRQContext<'irq_context>,
|
|
|
|
|
) {
|
|
|
|
@ -943,9 +943,9 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi
|
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|
|
+ state, synchronization,
|
|
|
|
|
+ synchronization::{IRQSafeNullLock, InitStateLock},
|
|
|
|
|
};
|
|
|
|
|
use register::{mmio::*, register_bitfields, register_structs};
|
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|
@@ -79,7 +80,7 @@
|
|
|
|
|
use tock_registers::{
|
|
|
|
|
interfaces::{Readable, Writeable},
|
|
|
|
|
@@ -83,7 +84,7 @@
|
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|
|
shared_registers: IRQSafeNullLock<SharedRegisters>,
|
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|
|
|
|
|
|
|
/// Access to banked registers is unguarded.
|
|
|
|
@ -954,7 +954,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
//--------------------------------------------------------------------------------------------------
|
|
|
|
|
@@ -116,6 +117,7 @@
|
|
|
|
|
@@ -120,6 +121,7 @@
|
|
|
|
|
//--------------------------------------------------------------------------------------------------
|
|
|
|
|
// Public Code
|
|
|
|
|
//--------------------------------------------------------------------------------------------------
|
|
|
|
@ -962,7 +962,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi
|
|
|
|
|
use synchronization::interface::Mutex;
|
|
|
|
|
|
|
|
|
|
impl GICD {
|
|
|
|
|
@@ -127,10 +129,17 @@
|
|
|
|
|
@@ -131,10 +133,17 @@
|
|
|
|
|
pub const unsafe fn new(mmio_start_addr: usize) -> Self {
|
|
|
|
|
Self {
|
|
|
|
|
shared_registers: IRQSafeNullLock::new(SharedRegisters::new(mmio_start_addr)),
|
|
|
|
@ -981,7 +981,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi
|
|
|
|
|
/// Use a banked ITARGETSR to retrieve the executing core's GIC target mask.
|
|
|
|
|
///
|
|
|
|
|
/// Quoting the GICv2 Architecture Specification:
|
|
|
|
|
@@ -138,7 +147,8 @@
|
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|
|
|
@@ -142,7 +151,8 @@
|
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|
|
|
/// "GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that
|
|
|
|
|
/// corresponds only to the processor reading the register."
|
|
|
|
|
fn local_gic_target_mask(&self) -> u32 {
|
|
|
|
@ -991,7 +991,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi
|
|
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|
|
}
|
|
|
|
|
|
|
|
|
|
/// Route all SPIs to the boot core and enable the distributor.
|
|
|
|
|
@@ -177,10 +187,10 @@
|
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|
|
@@ -181,10 +191,10 @@
|
|
|
|
|
// Check if we are handling a private or shared IRQ.
|
|
|
|
|
match irq_num {
|
|
|
|
|
// Private.
|
|
|
|
@ -1096,10 +1096,10 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
|
|
|
|
|
synchronization::IRQSafeNullLock,
|
|
|
|
|
};
|
|
|
|
|
+use core::sync::atomic::{AtomicUsize, Ordering};
|
|
|
|
|
use register::{mmio::*, register_bitfields, register_structs};
|
|
|
|
|
|
|
|
|
|
//--------------------------------------------------------------------------------------------------
|
|
|
|
|
@@ -117,6 +118,8 @@
|
|
|
|
|
use tock_registers::{
|
|
|
|
|
interfaces::{ReadWriteable, Writeable},
|
|
|
|
|
register_bitfields, register_structs,
|
|
|
|
|
@@ -121,6 +122,8 @@
|
|
|
|
|
|
|
|
|
|
/// Representation of the GPIO HW.
|
|
|
|
|
pub struct GPIO {
|
|
|
|
@ -1108,7 +1108,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
|
|
|
|
|
inner: IRQSafeNullLock<GPIOInner>,
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
@@ -136,6 +139,19 @@
|
|
|
|
|
@@ -140,6 +143,19 @@
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
@ -1128,7 +1128,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
|
|
|
|
|
/// Disable pull-up/down on pins 14 and 15.
|
|
|
|
|
#[cfg(feature = "bsp_rpi3")]
|
|
|
|
|
fn disable_pud_14_15_bcm2837(&mut self) {
|
|
|
|
|
@@ -190,10 +206,12 @@
|
|
|
|
|
@@ -194,10 +210,12 @@
|
|
|
|
|
///
|
|
|
|
|
/// # Safety
|
|
|
|
|
///
|
|
|
|
@ -1144,7 +1144,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
@@ -212,4 +230,26 @@
|
|
|
|
|
@@ -216,4 +234,26 @@
|
|
|
|
|
fn compatible(&self) -> &'static str {
|
|
|
|
|
"BCM GPIO"
|
|
|
|
|
}
|
|
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@ -1175,13 +1175,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
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diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_interrupt_controller/peripheral_ic.rs 14_virtual_mem_part2_mmio_remap/src/bsp/device_driver/bcm/bcm2xxx_interrupt_controller/peripheral_ic.rs
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--- 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_interrupt_controller/peripheral_ic.rs
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+++ 14_virtual_mem_part2_mmio_remap/src/bsp/device_driver/bcm/bcm2xxx_interrupt_controller/peripheral_ic.rs
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@@ -2,12 +2,12 @@
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//
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// Copyright (c) 2020-2021 Andre Richter <andre.o.richter@gmail.com>
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-//! Peripheral Interrupt regsler Driver.
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+//! Peripheral Interrupt Controller Driver.
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@@ -7,7 +7,7 @@
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use super::{InterruptController, PendingIRQs, PeripheralIRQ};
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use crate::{
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bsp::device_driver::common::MMIODerefWrapper,
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@ -1189,8 +1183,8 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
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+ driver, exception, memory, synchronization,
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synchronization::{IRQSafeNullLock, InitStateLock},
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};
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use register::{mmio::*, register_structs};
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@@ -51,11 +51,13 @@
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use tock_registers::{
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@@ -55,11 +55,13 @@
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/// Representation of the peripheral interrupt controller.
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pub struct PeripheralIC {
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@ -1205,7 +1199,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
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/// Stores registered IRQ handlers. Writable only during kernel init. RO afterwards.
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handler_table: InitStateLock<HandlerTable>,
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@@ -70,21 +72,26 @@
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@@ -74,21 +76,26 @@
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///
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/// # Safety
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///
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@ -1239,7 +1233,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
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}
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}
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@@ -93,6 +100,24 @@
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@@ -97,6 +104,24 @@
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//------------------------------------------------------------------------------
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use synchronization::interface::{Mutex, ReadWriteEx};
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@ -1322,10 +1316,10 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
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+ fmt,
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+ sync::atomic::{AtomicUsize, Ordering},
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+};
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use register::{mmio::*, register_bitfields, register_structs};
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//--------------------------------------------------------------------------------------------------
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@@ -232,6 +235,8 @@
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use tock_registers::{
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interfaces::{Readable, Writeable},
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register_bitfields, register_structs,
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@@ -237,6 +240,8 @@
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/// Representation of the UART.
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pub struct PL011Uart {
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@ -1334,7 +1328,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
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inner: IRQSafeNullLock<PL011UartInner>,
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irq_number: bsp::device_driver::IRQNumber,
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}
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@@ -271,7 +276,15 @@
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@@ -276,7 +281,15 @@
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/// genrated baud rate of `48_000_000 / (16 * 3.25) = 923_077`.
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///
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/// Error = `((923_077 - 921_600) / 921_600) * 100 = 0.16modulo`.
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@ -1351,7 +1345,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
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// Execution can arrive here while there are still characters queued in the TX FIFO and
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// actively being sent out by the UART hardware. If the UART is turned off in this case,
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// those queued characters would be lost.
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@@ -313,6 +326,8 @@
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@@ -318,6 +331,8 @@
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self.registers
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.CR
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.write(CR::UARTEN::Enabled + CR::TXE::Enabled + CR::RXE::Enabled);
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@ -1360,7 +1354,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
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}
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/// Send a character.
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@@ -390,13 +405,18 @@
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@@ -395,13 +410,18 @@
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///
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/// # Safety
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///
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@ -1382,7 +1376,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
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irq_number,
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}
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}
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@@ -413,7 +433,13 @@
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@@ -418,7 +438,13 @@
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}
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unsafe fn init(&self) -> Result<(), &'static str> {
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@ -1397,7 +1391,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
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Ok(())
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}
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@@ -432,6 +458,16 @@
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@@ -437,6 +463,16 @@
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Ok(())
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}
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@ -2155,16 +2149,15 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/driver.rs 14_virtual_mem_part2
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diff -uNr 13_exceptions_part2_peripheral_IRQs/src/lib.rs 14_virtual_mem_part2_mmio_remap/src/lib.rs
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--- 13_exceptions_part2_peripheral_IRQs/src/lib.rs
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+++ 14_virtual_mem_part2_mmio_remap/src/lib.rs
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@@ -109,6 +109,8 @@
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@@ -109,6 +109,7 @@
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#![allow(clippy::upper_case_acronyms)]
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#![allow(incomplete_features)]
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#![feature(asm)]
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+#![feature(const_evaluatable_checked)]
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+#![feature(const_fn)]
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#![feature(const_fn_fn_ptr_basics)]
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#![feature(const_fn_trait_bound)]
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#![feature(const_generics)]
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#![feature(const_panic)]
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@@ -129,6 +131,7 @@
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@@ -130,6 +131,7 @@
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mod synchronization;
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pub mod bsp;
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