From b23c4318f2edf83cc76ba5487afe7ffbfa2eb649 Mon Sep 17 00:00:00 2001 From: Andre Richter Date: Tue, 6 Jul 2021 23:02:20 +0200 Subject: [PATCH] Switch to tock-registers: Documentation and misc updates --- 02_runtime_init/README.md | 5 +- 05_drivers_gpio_uart/README.md | 25 ++-- 06_uart_chainloader/README.md | 8 +- 06_uart_chainloader/demo_payload_rpi3.img | Bin 6696 -> 6696 bytes 06_uart_chainloader/demo_payload_rpi4.img | Bin 6552 -> 6528 bytes 07_timestamps/README.md | 13 +- 09_privilege_level/README.md | 25 ++-- .../README.md | 15 ++- 11_exceptions_part1_groundwork/README.md | 14 +- 12_integrated_testing/README.md | 31 +++-- 13_exceptions_part2_peripheral_IRQs/README.md | 80 +++++++----- 14_virtual_mem_part2_mmio_remap/README.md | 123 +++++++++--------- .../README.md | 28 ++-- .../README.md | 28 ++-- X1_JTAG_boot/jtag_boot_rpi3.img | Bin 7856 -> 7840 bytes X1_JTAG_boot/jtag_boot_rpi4.img | Bin 6584 -> 6568 bytes 16 files changed, 216 insertions(+), 179 deletions(-) diff --git a/02_runtime_init/README.md b/02_runtime_init/README.md index 044a2d09..11ad00cc 100644 --- a/02_runtime_init/README.md +++ b/02_runtime_init/README.md @@ -40,14 +40,15 @@ diff -uNr 01_wait_forever/Cargo.toml 02_runtime_init/Cargo.toml authors = ["Andre Richter "] edition = "2018" -@@ -21,3 +21,7 @@ +@@ -21,3 +21,8 @@ ##-------------------------------------------------------------------------------------------------- [dependencies] + +# Platform specific dependencies +[target.'cfg(target_arch = "aarch64")'.dependencies] -+cortex-a = { version = "5.x.x" } ++cortex-a = { version = "6.x.x" } ++ diff -uNr 01_wait_forever/Makefile 02_runtime_init/Makefile --- 01_wait_forever/Makefile diff --git a/05_drivers_gpio_uart/README.md b/05_drivers_gpio_uart/README.md index 4125583e..7f0bbda5 100644 --- a/05_drivers_gpio_uart/README.md +++ b/05_drivers_gpio_uart/README.md @@ -126,8 +126,8 @@ diff -uNr 04_safe_globals/Cargo.toml 05_drivers_gpio_uart/Cargo.toml default = [] -bsp_rpi3 = [] -bsp_rpi4 = [] -+bsp_rpi3 = ["register"] -+bsp_rpi4 = ["register"] ++bsp_rpi3 = ["tock-registers"] ++bsp_rpi4 = ["tock-registers"] [[bin]] name = "kernel" @@ -136,11 +136,11 @@ diff -uNr 04_safe_globals/Cargo.toml 05_drivers_gpio_uart/Cargo.toml [dependencies] +# Optional dependencies -+register = { version = "1.x.x", optional = true } ++tock-registers = { version = "0.7.x", default-features = false, features = ["register_types"], optional = true } + # Platform specific dependencies [target.'cfg(target_arch = "aarch64")'.dependencies] - cortex-a = { version = "5.x.x" } + cortex-a = { version = "6.x.x" } diff -uNr 04_safe_globals/Makefile 05_drivers_gpio_uart/Makefile --- 04_safe_globals/Makefile @@ -220,7 +220,7 @@ diff -uNr 04_safe_globals/src/_arch/aarch64/cpu.rs 05_drivers_gpio_uart/src/_arc diff -uNr 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs --- 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs +++ 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs -@@ -0,0 +1,221 @@ +@@ -0,0 +1,225 @@ +// SPDX-License-Identifier: MIT OR Apache-2.0 +// +// Copyright (c) 2018-2021 Andre Richter @@ -231,7 +231,11 @@ diff -uNr 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 05_drivers_g + bsp::device_driver::common::MMIODerefWrapper, driver, synchronization, + synchronization::NullLock, +}; -+use register::{mmio::*, register_bitfields, register_structs}; ++use tock_registers::{ ++ interfaces::{ReadWriteable, Writeable}, ++ register_bitfields, register_structs, ++ registers::ReadWrite, ++}; + +//-------------------------------------------------------------------------------------------------- +// Private Definitions @@ -446,7 +450,7 @@ diff -uNr 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 05_drivers_g diff -uNr 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs --- 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs +++ 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs -@@ -0,0 +1,403 @@ +@@ -0,0 +1,408 @@ +// SPDX-License-Identifier: MIT OR Apache-2.0 +// +// Copyright (c) 2018-2021 Andre Richter @@ -463,7 +467,11 @@ diff -uNr 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 05_dri + synchronization::NullLock, +}; +use core::fmt; -+use register::{mmio::*, register_bitfields, register_structs}; ++use tock_registers::{ ++ interfaces::{Readable, Writeable}, ++ register_bitfields, register_structs, ++ registers::{ReadOnly, ReadWrite, WriteOnly}, ++}; + +//-------------------------------------------------------------------------------------------------- +// Private Definitions @@ -530,6 +538,7 @@ diff -uNr 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 05_dri + LCR_H [ + /// Word length. These bits indicate the number of data bits transmitted or received in a + /// frame. ++ #[allow(clippy::enum_variant_names)] + WLEN OFFSET(5) NUMBITS(2) [ + FiveBit = 0b00, + SixBit = 0b01, diff --git a/06_uart_chainloader/README.md b/06_uart_chainloader/README.md index a7239e8b..0f9e4aa6 100644 --- a/06_uart_chainloader/README.md +++ b/06_uart_chainloader/README.md @@ -279,7 +279,7 @@ diff -uNr 05_drivers_gpio_uart/src/_arch/aarch64/cpu/boot.s 06_uart_chainloader/ diff -uNr 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs --- 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs +++ 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs -@@ -144,7 +144,7 @@ +@@ -148,7 +148,7 @@ // Make an educated guess for a good delay value (Sequence described in the BCM2837 // peripherals PDF). // @@ -292,7 +292,7 @@ diff -uNr 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 06_uart diff -uNr 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs --- 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs +++ 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs -@@ -279,7 +279,7 @@ +@@ -284,7 +284,7 @@ } /// Retrieve a character. @@ -301,7 +301,7 @@ diff -uNr 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 0 // If RX FIFO is empty, if self.registers.FR.matches_all(FR::RXFE::SET) { // immediately return in non-blocking mode. -@@ -294,12 +294,7 @@ +@@ -299,12 +299,7 @@ } // Read one character. @@ -315,7 +315,7 @@ diff -uNr 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 0 // Update statistics. self.chars_read += 1; -@@ -379,14 +374,14 @@ +@@ -384,14 +379,14 @@ impl console::interface::Read for PL011Uart { fn read_char(&self) -> char { self.inner diff --git a/06_uart_chainloader/demo_payload_rpi3.img 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-344,7 +345,7 @@ diff -uNr 06_uart_chainloader/src/_arch/aarch64/time.rs 07_timestamps/src/_arch/ diff -uNr 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 07_timestamps/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs --- 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs +++ 07_timestamps/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs -@@ -139,25 +139,19 @@ +@@ -143,25 +143,19 @@ /// Disable pull-up/down on pins 14 and 15. #[cfg(feature = "bsp_rpi3")] fn disable_pud_14_15_bcm2837(&mut self) { @@ -380,7 +381,7 @@ diff -uNr 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 07_times diff -uNr 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 07_timestamps/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs --- 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs +++ 07_timestamps/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs -@@ -279,7 +279,7 @@ +@@ -284,7 +284,7 @@ } /// Retrieve a character. @@ -389,7 +390,7 @@ diff -uNr 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 07 // If RX FIFO is empty, if self.registers.FR.matches_all(FR::RXFE::SET) { // immediately return in non-blocking mode. -@@ -294,7 +294,12 @@ +@@ -299,7 +299,12 @@ } // Read one character. @@ -403,7 +404,7 @@ diff -uNr 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 07 // Update statistics. self.chars_read += 1; -@@ -374,14 +379,14 @@ +@@ -379,14 +384,14 @@ impl console::interface::Read for PL011Uart { fn read_char(&self) -> char { self.inner diff --git a/09_privilege_level/README.md b/09_privilege_level/README.md index 42ad905e..4b4c538d 100644 --- a/09_privilege_level/README.md +++ b/09_privilege_level/README.md @@ -211,11 +211,12 @@ diff -uNr 08_hw_debug_JTAG/Cargo.toml 09_privilege_level/Cargo.toml diff -uNr 08_hw_debug_JTAG/src/_arch/aarch64/cpu/boot.rs 09_privilege_level/src/_arch/aarch64/cpu/boot.rs --- 08_hw_debug_JTAG/src/_arch/aarch64/cpu/boot.rs +++ 09_privilege_level/src/_arch/aarch64/cpu/boot.rs -@@ -11,17 +11,67 @@ +@@ -11,17 +11,68 @@ //! //! crate::cpu::boot::arch_boot -+use cortex_a::{asm, regs::*}; ++use cortex_a::{asm, registers::*}; ++use tock_registers::interfaces::Writeable; + // Assembly counterpart to this file. global_asm!(include_str!("boot.s")); @@ -323,7 +324,7 @@ diff -uNr 08_hw_debug_JTAG/src/_arch/aarch64/cpu/boot.s 09_privilege_level/src/_ diff -uNr 08_hw_debug_JTAG/src/_arch/aarch64/exception/asynchronous.rs 09_privilege_level/src/_arch/aarch64/exception/asynchronous.rs --- 08_hw_debug_JTAG/src/_arch/aarch64/exception/asynchronous.rs +++ 09_privilege_level/src/_arch/aarch64/exception/asynchronous.rs -@@ -0,0 +1,81 @@ +@@ -0,0 +1,82 @@ +// SPDX-License-Identifier: MIT OR Apache-2.0 +// +// Copyright (c) 2018-2021 Andre Richter @@ -337,14 +338,15 @@ diff -uNr 08_hw_debug_JTAG/src/_arch/aarch64/exception/asynchronous.rs 09_privil +//! +//! crate::exception::asynchronous::arch_asynchronous + -+use cortex_a::regs::*; ++use cortex_a::registers::*; ++use tock_registers::interfaces::Readable; + +//-------------------------------------------------------------------------------------------------- +// Private Definitions +//-------------------------------------------------------------------------------------------------- + +trait DaifField { -+ fn daif_field() -> register::Field; ++ fn daif_field() -> tock_registers::fields::Field; +} + +struct Debug; @@ -357,25 +359,25 @@ diff -uNr 08_hw_debug_JTAG/src/_arch/aarch64/exception/asynchronous.rs 09_privil +//-------------------------------------------------------------------------------------------------- + +impl DaifField for Debug { -+ fn daif_field() -> register::Field { ++ fn daif_field() -> tock_registers::fields::Field { + DAIF::D + } +} + +impl DaifField for SError { -+ fn daif_field() -> register::Field { ++ fn daif_field() -> tock_registers::fields::Field { + DAIF::A + } +} + +impl DaifField for IRQ { -+ fn daif_field() -> register::Field { ++ fn daif_field() -> tock_registers::fields::Field { + DAIF::I + } +} + +impl DaifField for FIQ { -+ fn daif_field() -> register::Field { ++ fn daif_field() -> tock_registers::fields::Field { + DAIF::F + } +} @@ -409,7 +411,7 @@ diff -uNr 08_hw_debug_JTAG/src/_arch/aarch64/exception/asynchronous.rs 09_privil diff -uNr 08_hw_debug_JTAG/src/_arch/aarch64/exception.rs 09_privilege_level/src/_arch/aarch64/exception.rs --- 08_hw_debug_JTAG/src/_arch/aarch64/exception.rs +++ 09_privilege_level/src/_arch/aarch64/exception.rs -@@ -0,0 +1,30 @@ +@@ -0,0 +1,31 @@ +// SPDX-License-Identifier: MIT OR Apache-2.0 +// +// Copyright (c) 2018-2021 Andre Richter @@ -423,7 +425,8 @@ diff -uNr 08_hw_debug_JTAG/src/_arch/aarch64/exception.rs 09_privilege_level/src +//! +//! crate::exception::arch_exception + -+use cortex_a::regs::*; ++use cortex_a::registers::*; ++use tock_registers::interfaces::Readable; + +//-------------------------------------------------------------------------------------------------- +// Public Code diff --git a/10_virtual_mem_part1_identity_mapping/README.md b/10_virtual_mem_part1_identity_mapping/README.md index f573de03..9b16747d 100644 --- a/10_virtual_mem_part1_identity_mapping/README.md +++ b/10_virtual_mem_part1_identity_mapping/README.md @@ -364,7 +364,7 @@ diff -uNr 09_privilege_level/Cargo.toml 10_virtual_mem_part1_identity_mapping/Ca diff -uNr 09_privilege_level/src/_arch/aarch64/memory/mmu/translation_table.rs 10_virtual_mem_part1_identity_mapping/src/_arch/aarch64/memory/mmu/translation_table.rs --- 09_privilege_level/src/_arch/aarch64/memory/mmu/translation_table.rs +++ 10_virtual_mem_part1_identity_mapping/src/_arch/aarch64/memory/mmu/translation_table.rs -@@ -0,0 +1,288 @@ +@@ -0,0 +1,292 @@ +// SPDX-License-Identifier: MIT OR Apache-2.0 +// +// Copyright (c) 2021 Andre Richter @@ -388,7 +388,11 @@ diff -uNr 09_privilege_level/src/_arch/aarch64/memory/mmu/translation_table.rs 1 + }, +}; +use core::convert; -+use register::{register_bitfields, InMemoryRegister}; ++use tock_registers::{ ++ interfaces::{Readable, Writeable}, ++ register_bitfields, ++ registers::InMemoryRegister, ++}; + +//-------------------------------------------------------------------------------------------------- +// Private Definitions @@ -549,7 +553,7 @@ diff -uNr 09_privilege_level/src/_arch/aarch64/memory/mmu/translation_table.rs 1 + +/// Convert the kernel's generic memory attributes to HW-specific attributes of the MMU. +impl convert::From -+ for register::FieldValue ++ for tock_registers::fields::FieldValue +{ + fn from(attribute_fields: AttributeFields) -> Self { + // Memory attributes. @@ -657,7 +661,7 @@ diff -uNr 09_privilege_level/src/_arch/aarch64/memory/mmu/translation_table.rs 1 diff -uNr 09_privilege_level/src/_arch/aarch64/memory/mmu.rs 10_virtual_mem_part1_identity_mapping/src/_arch/aarch64/memory/mmu.rs --- 09_privilege_level/src/_arch/aarch64/memory/mmu.rs +++ 10_virtual_mem_part1_identity_mapping/src/_arch/aarch64/memory/mmu.rs -@@ -0,0 +1,164 @@ +@@ -0,0 +1,165 @@ +// SPDX-License-Identifier: MIT OR Apache-2.0 +// +// Copyright (c) 2018-2021 Andre Richter @@ -678,7 +682,8 @@ diff -uNr 09_privilege_level/src/_arch/aarch64/memory/mmu.rs 10_virtual_mem_part + memory::mmu::{translation_table::KernelTranslationTable, TranslationGranule}, +}; +use core::intrinsics::unlikely; -+use cortex_a::{barrier, regs::*}; ++use cortex_a::{asm::barrier, registers::*}; ++use tock_registers::interfaces::{ReadWriteable, Readable, Writeable}; + +//-------------------------------------------------------------------------------------------------- +// Private Definitions diff --git a/11_exceptions_part1_groundwork/README.md b/11_exceptions_part1_groundwork/README.md index 77a45ec6..df8ecd6f 100644 --- a/11_exceptions_part1_groundwork/README.md +++ b/11_exceptions_part1_groundwork/README.md @@ -492,14 +492,18 @@ diff -uNr 10_virtual_mem_part1_identity_mapping/Cargo.toml 11_exceptions_part1_g diff -uNr 10_virtual_mem_part1_identity_mapping/src/_arch/aarch64/exception.rs 11_exceptions_part1_groundwork/src/_arch/aarch64/exception.rs --- 10_virtual_mem_part1_identity_mapping/src/_arch/aarch64/exception.rs +++ 11_exceptions_part1_groundwork/src/_arch/aarch64/exception.rs -@@ -11,7 +11,224 @@ +@@ -11,8 +11,227 @@ //! //! crate::exception::arch_exception --use cortex_a::regs::*; +-use cortex_a::registers::*; +-use tock_registers::interfaces::Readable; +use core::{cell::UnsafeCell, fmt}; -+use cortex_a::{asm, barrier, regs::*}; -+use register::InMemoryRegister; ++use cortex_a::{asm, asm::barrier, registers::*}; ++use tock_registers::{ ++ interfaces::{Readable, Writeable}, ++ registers::InMemoryRegister, ++}; + +// Assembly counterpart to this file. +global_asm!(include_str!("exception.s")); @@ -718,7 +722,7 @@ diff -uNr 10_virtual_mem_part1_identity_mapping/src/_arch/aarch64/exception.rs 1 //-------------------------------------------------------------------------------------------------- // Public Code -@@ -28,3 +245,23 @@ +@@ -29,3 +248,23 @@ _ => (PrivilegeLevel::Unknown, "Unknown"), } } diff --git a/12_integrated_testing/README.md b/12_integrated_testing/README.md index d252d0c2..bb1677e9 100644 --- a/12_integrated_testing/README.md +++ b/12_integrated_testing/README.md @@ -825,10 +825,10 @@ diff -uNr 11_exceptions_part1_groundwork/Cargo.toml 12_integrated_testing/Cargo. authors = ["Andre Richter "] edition = "2018" -@@ -11,20 +11,46 @@ +@@ -11,21 +11,46 @@ default = [] - bsp_rpi3 = ["register"] - bsp_rpi4 = ["register"] + bsp_rpi3 = ["tock-registers"] + bsp_rpi4 = ["tock-registers"] - -[[bin]] -name = "kernel" @@ -843,14 +843,13 @@ diff -uNr 11_exceptions_part1_groundwork/Cargo.toml 12_integrated_testing/Cargo. +test-types = { path = "test-types" } # Optional dependencies --register = { version = "1.x.x", optional = true } -+register = { version = "1.x.x", features = ["no_std_unit_tests"], optional = true } -+qemu-exit = { version = "1.x.x", optional = true } + tock-registers = { version = "0.7.x", default-features = false, features = ["register_types"], optional = true } ++qemu-exit = { version = "2.x.x", optional = true } # Platform specific dependencies [target.'cfg(target_arch = "aarch64")'.dependencies] - cortex-a = { version = "5.x.x" } -+ + cortex-a = { version = "6.x.x" } + +##-------------------------------------------------------------------------------------------------- +## Testing +##-------------------------------------------------------------------------------------------------- @@ -1010,12 +1009,12 @@ diff -uNr 11_exceptions_part1_groundwork/src/_arch/aarch64/exception.rs 12_integ //! crate::exception::arch_exception use core::{cell::UnsafeCell, fmt}; --use cortex_a::{asm, barrier, regs::*}; -+use cortex_a::{barrier, regs::*}; - use register::InMemoryRegister; - - // Assembly counterpart to this file. -@@ -87,16 +87,6 @@ +-use cortex_a::{asm, asm::barrier, registers::*}; ++use cortex_a::{asm::barrier, registers::*}; + use tock_registers::{ + interfaces::{Readable, Writeable}, + registers::InMemoryRegister, +@@ -90,16 +90,6 @@ #[no_mangle] unsafe extern "C" fn current_elx_synchronous(e: &mut ExceptionContext) { @@ -1036,7 +1035,7 @@ diff -uNr 11_exceptions_part1_groundwork/src/_arch/aarch64/exception.rs 12_integ diff -uNr 11_exceptions_part1_groundwork/src/_arch/aarch64/memory/mmu/translation_table.rs 12_integrated_testing/src/_arch/aarch64/memory/mmu/translation_table.rs --- 11_exceptions_part1_groundwork/src/_arch/aarch64/memory/mmu/translation_table.rs +++ 12_integrated_testing/src/_arch/aarch64/memory/mmu/translation_table.rs -@@ -286,3 +286,31 @@ +@@ -290,3 +290,31 @@ self.lvl2.phys_start_addr_u64() } } @@ -1072,7 +1071,7 @@ diff -uNr 11_exceptions_part1_groundwork/src/_arch/aarch64/memory/mmu/translatio diff -uNr 11_exceptions_part1_groundwork/src/_arch/aarch64/memory/mmu.rs 12_integrated_testing/src/_arch/aarch64/memory/mmu.rs --- 11_exceptions_part1_groundwork/src/_arch/aarch64/memory/mmu.rs +++ 12_integrated_testing/src/_arch/aarch64/memory/mmu.rs -@@ -162,3 +162,33 @@ +@@ -163,3 +163,33 @@ SCTLR_EL1.matches_all(SCTLR_EL1::M::Enable) } } diff --git a/13_exceptions_part2_peripheral_IRQs/README.md b/13_exceptions_part2_peripheral_IRQs/README.md index 1174ca9e..02341a12 100644 --- a/13_exceptions_part2_peripheral_IRQs/README.md +++ b/13_exceptions_part2_peripheral_IRQs/README.md @@ -761,7 +761,7 @@ diff -uNr 12_integrated_testing/Cargo.toml 13_exceptions_part2_peripheral_IRQs/C diff -uNr 12_integrated_testing/src/_arch/aarch64/cpu/smp.rs 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/cpu/smp.rs --- 12_integrated_testing/src/_arch/aarch64/cpu/smp.rs +++ 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/cpu/smp.rs -@@ -0,0 +1,29 @@ +@@ -0,0 +1,30 @@ +// SPDX-License-Identifier: MIT OR Apache-2.0 +// +// Copyright (c) 2018-2021 Andre Richter @@ -775,7 +775,8 @@ diff -uNr 12_integrated_testing/src/_arch/aarch64/cpu/smp.rs 13_exceptions_part2 +//! +//! crate::cpu::smp::arch_smp + -+use cortex_a::regs::*; ++use cortex_a::registers::*; ++use tock_registers::interfaces::Readable; + +//-------------------------------------------------------------------------------------------------- +// Public Code @@ -795,7 +796,14 @@ diff -uNr 12_integrated_testing/src/_arch/aarch64/cpu/smp.rs 13_exceptions_part2 diff -uNr 12_integrated_testing/src/_arch/aarch64/exception/asynchronous.rs 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/exception/asynchronous.rs --- 12_integrated_testing/src/_arch/aarch64/exception/asynchronous.rs +++ 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/exception/asynchronous.rs -@@ -17,6 +17,10 @@ +@@ -12,12 +12,16 @@ + //! crate::exception::asynchronous::arch_asynchronous + + use cortex_a::registers::*; +-use tock_registers::interfaces::Readable; ++use tock_registers::interfaces::{Readable, Writeable}; + + //-------------------------------------------------------------------------------------------------- // Private Definitions //-------------------------------------------------------------------------------------------------- @@ -804,9 +812,9 @@ diff -uNr 12_integrated_testing/src/_arch/aarch64/exception/asynchronous.rs 13_e +} + trait DaifField { - fn daif_field() -> register::Field; + fn daif_field() -> tock_registers::fields::Field; } -@@ -65,6 +69,71 @@ +@@ -66,6 +70,71 @@ // Public Code //-------------------------------------------------------------------------------------------------- @@ -888,9 +896,9 @@ diff -uNr 12_integrated_testing/src/_arch/aarch64/exception.rs 13_exceptions_par +use crate::{bsp, exception}; use core::{cell::UnsafeCell, fmt}; - use cortex_a::{barrier, regs::*}; - use register::InMemoryRegister; -@@ -91,8 +92,11 @@ + use cortex_a::{asm::barrier, registers::*}; + use tock_registers::{ +@@ -94,8 +95,11 @@ } #[no_mangle] @@ -908,7 +916,7 @@ diff -uNr 12_integrated_testing/src/_arch/aarch64/exception.rs 13_exceptions_par diff -uNr 12_integrated_testing/src/bsp/device_driver/arm/gicv2/gicc.rs 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gicc.rs --- 12_integrated_testing/src/bsp/device_driver/arm/gicv2/gicc.rs +++ 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gicc.rs -@@ -0,0 +1,137 @@ +@@ -0,0 +1,141 @@ +// SPDX-License-Identifier: MIT OR Apache-2.0 +// +// Copyright (c) 2020-2021 Andre Richter @@ -916,7 +924,11 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/arm/gicv2/gicc.rs 13_excep +//! GICC Driver - GIC CPU interface. + +use crate::{bsp::device_driver::common::MMIODerefWrapper, exception}; -+use register::{mmio::*, register_bitfields, register_structs}; ++use tock_registers::{ ++ interfaces::{Readable, Writeable}, ++ register_bitfields, register_structs, ++ registers::ReadWrite, ++}; + +//-------------------------------------------------------------------------------------------------- +// Private Definitions @@ -1050,7 +1062,7 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/arm/gicv2/gicc.rs 13_excep diff -uNr 12_integrated_testing/src/bsp/device_driver/arm/gicv2/gicd.rs 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gicd.rs --- 12_integrated_testing/src/bsp/device_driver/arm/gicv2/gicd.rs +++ 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gicd.rs -@@ -0,0 +1,195 @@ +@@ -0,0 +1,199 @@ +// SPDX-License-Identifier: MIT OR Apache-2.0 +// +// Copyright (c) 2020-2021 Andre Richter @@ -1064,7 +1076,11 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/arm/gicv2/gicd.rs 13_excep + bsp::device_driver::common::MMIODerefWrapper, state, synchronization, + synchronization::IRQSafeNullLock, +}; -+use register::{mmio::*, register_bitfields, register_structs}; ++use tock_registers::{ ++ interfaces::{Readable, Writeable}, ++ register_bitfields, register_structs, ++ registers::{ReadOnly, ReadWrite}, ++}; + +//-------------------------------------------------------------------------------------------------- +// Private Definitions @@ -1495,9 +1511,9 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 13_exc - synchronization::NullLock, + synchronization::IRQSafeNullLock, }; - use register::{mmio::*, register_bitfields, register_structs}; - -@@ -117,7 +117,7 @@ + use tock_registers::{ + interfaces::{ReadWriteable, Writeable}, +@@ -121,7 +121,7 @@ /// Representation of the GPIO HW. pub struct GPIO { @@ -1506,7 +1522,7 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 13_exc } //-------------------------------------------------------------------------------------------------- -@@ -193,7 +193,7 @@ +@@ -197,7 +197,7 @@ /// - The user must ensure to provide a correct MMIO start address. pub const unsafe fn new(mmio_start_addr: usize) -> Self { Self { @@ -1519,12 +1535,12 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 13_exc diff -uNr 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_interrupt_controller/peripheral_ic.rs 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_interrupt_controller/peripheral_ic.rs --- 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_interrupt_controller/peripheral_ic.rs +++ 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_interrupt_controller/peripheral_ic.rs -@@ -0,0 +1,163 @@ +@@ -0,0 +1,167 @@ +// SPDX-License-Identifier: MIT OR Apache-2.0 +// +// Copyright (c) 2020-2021 Andre Richter + -+//! Peripheral Interrupt regsler Driver. ++//! Peripheral Interrupt Controller Driver. + +use super::{InterruptController, PendingIRQs, PeripheralIRQ}; +use crate::{ @@ -1532,7 +1548,11 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_interrupt_cont + exception, synchronization, + synchronization::{IRQSafeNullLock, InitStateLock}, +}; -+use register::{mmio::*, register_structs}; ++use tock_registers::{ ++ interfaces::{Readable, Writeable}, ++ register_structs, ++ registers::{ReadOnly, WriteOnly}, ++}; + +//-------------------------------------------------------------------------------------------------- +// Private Definitions @@ -1833,8 +1853,8 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs + synchronization, synchronization::IRQSafeNullLock, }; use core::fmt; - use register::{mmio::*, register_bitfields, register_structs}; -@@ -135,6 +135,52 @@ + use tock_registers::{ +@@ -140,6 +140,52 @@ ] ], @@ -1887,7 +1907,7 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs /// Interrupt Clear Register. ICR [ /// Meta field for all pending interrupts. -@@ -153,7 +199,10 @@ +@@ -158,7 +204,10 @@ (0x28 => FBRD: WriteOnly), (0x2c => LCR_H: WriteOnly), (0x30 => CR: WriteOnly), @@ -1899,7 +1919,7 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs (0x44 => ICR: WriteOnly), (0x48 => @END), } -@@ -183,7 +232,8 @@ +@@ -188,7 +237,8 @@ /// Representation of the UART. pub struct PL011Uart { @@ -1909,7 +1929,7 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs } //-------------------------------------------------------------------------------------------------- -@@ -251,6 +301,14 @@ +@@ -256,6 +306,14 @@ .LCR_H .write(LCR_H::WLEN::EightBit + LCR_H::FEN::FifosEnabled); @@ -1924,7 +1944,7 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs // Turn the UART on. self.registers .CR -@@ -333,9 +391,13 @@ +@@ -338,9 +396,13 @@ /// # Safety /// /// - The user must ensure to provide a correct MMIO start address. @@ -1940,7 +1960,7 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs } } } -@@ -355,6 +417,21 @@ +@@ -360,6 +422,21 @@ Ok(()) } @@ -1962,7 +1982,7 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs } impl console::interface::Write for PL011Uart { -@@ -401,3 +478,24 @@ +@@ -406,3 +483,24 @@ self.inner.lock(|inner| inner.chars_read) } } @@ -2376,15 +2396,17 @@ diff -uNr 12_integrated_testing/src/exception/asynchronous.rs 13_exceptions_part diff -uNr 12_integrated_testing/src/lib.rs 13_exceptions_part2_peripheral_IRQs/src/lib.rs --- 12_integrated_testing/src/lib.rs +++ 13_exceptions_part2_peripheral_IRQs/src/lib.rs -@@ -108,6 +108,7 @@ +@@ -108,7 +108,9 @@ #![allow(clippy::upper_case_acronyms)] #![allow(incomplete_features)] +#![feature(asm)] #![feature(const_fn_fn_ptr_basics)] ++#![feature(const_fn_trait_bound)] #![feature(const_generics)] #![feature(const_panic)] -@@ -134,6 +135,7 @@ + #![feature(core_intrinsics)] +@@ -134,6 +136,7 @@ pub mod exception; pub mod memory; pub mod print; diff --git a/14_virtual_mem_part2_mmio_remap/README.md b/14_virtual_mem_part2_mmio_remap/README.md index 73ef83a3..6cb7e16f 100644 --- a/14_virtual_mem_part2_mmio_remap/README.md +++ b/14_virtual_mem_part2_mmio_remap/README.md @@ -397,9 +397,9 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/exception.rs 14_ + memory::Address, +}; use core::{cell::UnsafeCell, fmt}; - use cortex_a::{barrier, regs::*}; - use register::InMemoryRegister; -@@ -50,6 +54,20 @@ + use cortex_a::{asm::barrier, registers::*}; + use tock_registers::{ +@@ -53,6 +57,20 @@ // Private Code //-------------------------------------------------------------------------------------------------- @@ -420,7 +420,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/exception.rs 14_ /// Prints verbose information about the exception and then panics. fn default_exception_handler(e: &ExceptionContext) { panic!( -@@ -166,7 +184,9 @@ +@@ -169,7 +187,9 @@ writeln!(f, " - {}", ec_translation)?; // Raw print of instruction specific syndrome. @@ -451,7 +451,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu/trans }, }; use core::convert; -@@ -117,12 +120,9 @@ +@@ -121,12 +124,9 @@ } trait StartAddr { @@ -465,7 +465,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu/trans //-------------------------------------------------------------------------------------------------- // Public Definitions //-------------------------------------------------------------------------------------------------- -@@ -137,10 +137,13 @@ +@@ -141,10 +141,13 @@ /// Table descriptors, covering 512 MiB windows. lvl2: [TableDescriptor; NUM_TABLES], @@ -482,7 +482,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu/trans //-------------------------------------------------------------------------------------------------- // Private Code -@@ -148,12 +151,8 @@ +@@ -152,12 +155,8 @@ // The binary is still identity mapped, so we don't need to convert here. impl StartAddr for [T; N] { @@ -497,7 +497,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu/trans } } -@@ -166,10 +165,10 @@ +@@ -170,10 +169,10 @@ } /// Create an instance pointing to the supplied address. @@ -510,7 +510,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu/trans val.write( STAGE1_TABLE_DESCRIPTOR::NEXT_LEVEL_TABLE_ADDR_64KiB.val(shifted as u64) + STAGE1_TABLE_DESCRIPTOR::TYPE::Table -@@ -226,7 +225,10 @@ +@@ -230,7 +229,10 @@ } /// Create an instance. @@ -522,7 +522,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu/trans let val = InMemoryRegister::::new(0); let shifted = phys_output_addr as u64 >> Granule64KiB::SHIFT; -@@ -240,50 +242,193 @@ +@@ -244,50 +246,193 @@ Self { value: val.get() } } @@ -687,7 +687,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu/trans + return Err("Virtual page is already mapped"); } + -+ *page_descriptor = PageDescriptor::from_output_addr(phys_page.as_ptr(), &attr); ++ *page_descriptor = PageDescriptor::from_output_addr(phys_page.as_ptr(), attr); } Ok(()) @@ -733,7 +733,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu/trans } } -@@ -292,6 +437,9 @@ +@@ -296,6 +441,9 @@ //-------------------------------------------------------------------------------------------------- #[cfg(test)] @@ -755,8 +755,8 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu.rs 14 + memory::{mmu::TranslationGranule, Address, Physical}, }; use core::intrinsics::unlikely; - use cortex_a::{barrier, regs::*}; -@@ -45,13 +45,6 @@ + use cortex_a::{asm::barrier, registers::*}; +@@ -46,13 +46,6 @@ // Global instances //-------------------------------------------------------------------------------------------------- @@ -770,7 +770,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu.rs 14 static MMU: MemoryManagementUnit = MemoryManagementUnit; //-------------------------------------------------------------------------------------------------- -@@ -86,7 +79,7 @@ +@@ -87,7 +80,7 @@ /// Configure various settings of stage 1 of the EL1 translation regime. fn configure_translation_control(&self) { @@ -779,7 +779,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu.rs 14 TCR_EL1.write( TCR_EL1::TBI0::Used -@@ -118,7 +111,10 @@ +@@ -119,7 +112,10 @@ use memory::mmu::MMUEnableError; impl memory::mmu::interface::MMU for MemoryManagementUnit { @@ -791,7 +791,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu.rs 14 if unlikely(self.is_enabled()) { return Err(MMUEnableError::AlreadyEnabled); } -@@ -133,13 +129,8 @@ +@@ -134,13 +130,8 @@ // Prepare the memory attribute indirection register. self.set_up_mair(); @@ -806,7 +806,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu.rs 14 self.configure_translation_control(); -@@ -162,33 +153,3 @@ +@@ -163,33 +154,3 @@ SCTLR_EL1.matches_all(SCTLR_EL1::M::Enable) } } @@ -852,10 +852,10 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi +use crate::{ + bsp::device_driver::common::MMIODerefWrapper, exception, synchronization::InitStateLock, +}; - use register::{mmio::*, register_bitfields, register_structs}; - - //-------------------------------------------------------------------------------------------------- -@@ -56,12 +58,13 @@ + use tock_registers::{ + interfaces::{Readable, Writeable}, + register_bitfields, register_structs, +@@ -60,12 +62,13 @@ /// Representation of the GIC CPU interface. pub struct GICC { @@ -870,7 +870,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi impl GICC { /// Create an instance. -@@ -71,10 +74,15 @@ +@@ -75,10 +78,15 @@ /// - The user must ensure to provide a correct MMIO start address. pub const unsafe fn new(mmio_start_addr: usize) -> Self { Self { @@ -887,7 +887,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi /// Accept interrupts of any priority. /// /// Quoting the GICv2 Architecture Specification: -@@ -87,7 +95,9 @@ +@@ -91,7 +99,9 @@ /// - GICC MMIO registers are banked per CPU core. It is therefore safe to have `&self` instead /// of `&mut self`. pub fn priority_accept_all(&self) { @@ -898,7 +898,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi } /// Enable the interface - start accepting IRQs. -@@ -97,7 +107,9 @@ +@@ -101,7 +111,9 @@ /// - GICC MMIO registers are banked per CPU core. It is therefore safe to have `&self` instead /// of `&mut self`. pub fn enable(&self) { @@ -909,7 +909,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi } /// Extract the number of the highest-priority pending IRQ. -@@ -113,7 +125,8 @@ +@@ -117,7 +129,8 @@ &self, _ic: &exception::asynchronous::IRQContext<'irq_context>, ) -> usize { @@ -919,7 +919,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi } /// Complete handling of the currently active IRQ. -@@ -132,6 +145,8 @@ +@@ -136,6 +149,8 @@ irq_number: u32, _ic: &exception::asynchronous::IRQContext<'irq_context>, ) { @@ -943,9 +943,9 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi + state, synchronization, + synchronization::{IRQSafeNullLock, InitStateLock}, }; - use register::{mmio::*, register_bitfields, register_structs}; - -@@ -79,7 +80,7 @@ + use tock_registers::{ + interfaces::{Readable, Writeable}, +@@ -83,7 +84,7 @@ shared_registers: IRQSafeNullLock, /// Access to banked registers is unguarded. @@ -954,7 +954,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi } //-------------------------------------------------------------------------------------------------- -@@ -116,6 +117,7 @@ +@@ -120,6 +121,7 @@ //-------------------------------------------------------------------------------------------------- // Public Code //-------------------------------------------------------------------------------------------------- @@ -962,7 +962,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi use synchronization::interface::Mutex; impl GICD { -@@ -127,10 +129,17 @@ +@@ -131,10 +133,17 @@ pub const unsafe fn new(mmio_start_addr: usize) -> Self { Self { shared_registers: IRQSafeNullLock::new(SharedRegisters::new(mmio_start_addr)), @@ -981,7 +981,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi /// Use a banked ITARGETSR to retrieve the executing core's GIC target mask. /// /// Quoting the GICv2 Architecture Specification: -@@ -138,7 +147,8 @@ +@@ -142,7 +151,8 @@ /// "GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that /// corresponds only to the processor reading the register." fn local_gic_target_mask(&self) -> u32 { @@ -991,7 +991,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi } /// Route all SPIs to the boot core and enable the distributor. -@@ -177,10 +187,10 @@ +@@ -181,10 +191,10 @@ // Check if we are handling a private or shared IRQ. match irq_num { // Private. @@ -1096,10 +1096,10 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_ synchronization::IRQSafeNullLock, }; +use core::sync::atomic::{AtomicUsize, Ordering}; - use register::{mmio::*, register_bitfields, register_structs}; - - //-------------------------------------------------------------------------------------------------- -@@ -117,6 +118,8 @@ + use tock_registers::{ + interfaces::{ReadWriteable, Writeable}, + register_bitfields, register_structs, +@@ -121,6 +122,8 @@ /// Representation of the GPIO HW. pub struct GPIO { @@ -1108,7 +1108,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_ inner: IRQSafeNullLock, } -@@ -136,6 +139,19 @@ +@@ -140,6 +143,19 @@ } } @@ -1128,7 +1128,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_ /// Disable pull-up/down on pins 14 and 15. #[cfg(feature = "bsp_rpi3")] fn disable_pud_14_15_bcm2837(&mut self) { -@@ -190,10 +206,12 @@ +@@ -194,10 +210,12 @@ /// /// # Safety /// @@ -1144,7 +1144,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_ } } -@@ -212,4 +230,26 @@ +@@ -216,4 +234,26 @@ fn compatible(&self) -> &'static str { "BCM GPIO" } @@ -1175,13 +1175,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_interrupt_controller/peripheral_ic.rs 14_virtual_mem_part2_mmio_remap/src/bsp/device_driver/bcm/bcm2xxx_interrupt_controller/peripheral_ic.rs --- 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_interrupt_controller/peripheral_ic.rs +++ 14_virtual_mem_part2_mmio_remap/src/bsp/device_driver/bcm/bcm2xxx_interrupt_controller/peripheral_ic.rs -@@ -2,12 +2,12 @@ - // - // Copyright (c) 2020-2021 Andre Richter - --//! Peripheral Interrupt regsler Driver. -+//! Peripheral Interrupt Controller Driver. - +@@ -7,7 +7,7 @@ use super::{InterruptController, PendingIRQs, PeripheralIRQ}; use crate::{ bsp::device_driver::common::MMIODerefWrapper, @@ -1189,8 +1183,8 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_ + driver, exception, memory, synchronization, synchronization::{IRQSafeNullLock, InitStateLock}, }; - use register::{mmio::*, register_structs}; -@@ -51,11 +51,13 @@ + use tock_registers::{ +@@ -55,11 +55,13 @@ /// Representation of the peripheral interrupt controller. pub struct PeripheralIC { @@ -1205,7 +1199,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_ /// Stores registered IRQ handlers. Writable only during kernel init. RO afterwards. handler_table: InitStateLock, -@@ -70,21 +72,26 @@ +@@ -74,21 +76,26 @@ /// /// # Safety /// @@ -1239,7 +1233,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_ } } -@@ -93,6 +100,24 @@ +@@ -97,6 +104,24 @@ //------------------------------------------------------------------------------ use synchronization::interface::{Mutex, ReadWriteEx}; @@ -1322,10 +1316,10 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_ + fmt, + sync::atomic::{AtomicUsize, Ordering}, +}; - use register::{mmio::*, register_bitfields, register_structs}; - - //-------------------------------------------------------------------------------------------------- -@@ -232,6 +235,8 @@ + use tock_registers::{ + interfaces::{Readable, Writeable}, + register_bitfields, register_structs, +@@ -237,6 +240,8 @@ /// Representation of the UART. pub struct PL011Uart { @@ -1334,7 +1328,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_ inner: IRQSafeNullLock, irq_number: bsp::device_driver::IRQNumber, } -@@ -271,7 +276,15 @@ +@@ -276,7 +281,15 @@ /// genrated baud rate of `48_000_000 / (16 * 3.25) = 923_077`. /// /// Error = `((923_077 - 921_600) / 921_600) * 100 = 0.16modulo`. @@ -1351,7 +1345,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_ // Execution can arrive here while there are still characters queued in the TX FIFO and // actively being sent out by the UART hardware. If the UART is turned off in this case, // those queued characters would be lost. -@@ -313,6 +326,8 @@ +@@ -318,6 +331,8 @@ self.registers .CR .write(CR::UARTEN::Enabled + CR::TXE::Enabled + CR::RXE::Enabled); @@ -1360,7 +1354,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_ } /// Send a character. -@@ -390,13 +405,18 @@ +@@ -395,13 +410,18 @@ /// /// # Safety /// @@ -1382,7 +1376,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_ irq_number, } } -@@ -413,7 +433,13 @@ +@@ -418,7 +438,13 @@ } unsafe fn init(&self) -> Result<(), &'static str> { @@ -1397,7 +1391,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_ Ok(()) } -@@ -432,6 +458,16 @@ +@@ -437,6 +463,16 @@ Ok(()) } @@ -2155,16 +2149,15 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/driver.rs 14_virtual_mem_part2 diff -uNr 13_exceptions_part2_peripheral_IRQs/src/lib.rs 14_virtual_mem_part2_mmio_remap/src/lib.rs --- 13_exceptions_part2_peripheral_IRQs/src/lib.rs +++ 14_virtual_mem_part2_mmio_remap/src/lib.rs -@@ -109,6 +109,8 @@ +@@ -109,6 +109,7 @@ #![allow(clippy::upper_case_acronyms)] #![allow(incomplete_features)] #![feature(asm)] +#![feature(const_evaluatable_checked)] -+#![feature(const_fn)] #![feature(const_fn_fn_ptr_basics)] + #![feature(const_fn_trait_bound)] #![feature(const_generics)] - #![feature(const_panic)] -@@ -129,6 +131,7 @@ +@@ -130,6 +131,7 @@ mod synchronization; pub mod bsp; diff --git a/15_virtual_mem_part3_precomputed_tables/README.md b/15_virtual_mem_part3_precomputed_tables/README.md index c04cb3d2..581dcefc 100644 --- a/15_virtual_mem_part3_precomputed_tables/README.md +++ b/15_virtual_mem_part3_precomputed_tables/README.md @@ -802,10 +802,10 @@ diff -uNr 14_virtual_mem_part2_mmio_remap/src/_arch/aarch64/cpu/boot.rs 15_virtu +use crate::{cpu, memory, memory::Address}; +use core::intrinsics::unlikely; - use cortex_a::{asm, regs::*}; + use cortex_a::{asm, registers::*}; + use tock_registers::interfaces::Writeable; - // Assembly counterpart to this file. -@@ -69,9 +71,18 @@ +@@ -70,9 +72,18 @@ /// /// - Exception return from EL2 must must continue execution in EL1 with `kernel_init()`. #[no_mangle] @@ -857,10 +857,10 @@ diff -uNr 14_virtual_mem_part2_mmio_remap/src/_arch/aarch64/memory/mmu/translati }; -use core::convert; +use core::convert::{self, TryInto}; - use register::{register_bitfields, InMemoryRegister}; - - //-------------------------------------------------------------------------------------------------- -@@ -120,7 +120,7 @@ + use tock_registers::{ + interfaces::{Readable, Writeable}, + register_bitfields, +@@ -124,7 +124,7 @@ } trait StartAddr { @@ -869,7 +869,7 @@ diff -uNr 14_virtual_mem_part2_mmio_remap/src/_arch/aarch64/memory/mmu/translati } //-------------------------------------------------------------------------------------------------- -@@ -149,9 +149,8 @@ +@@ -153,9 +153,8 @@ // Private Code //-------------------------------------------------------------------------------------------------- @@ -880,7 +880,7 @@ diff -uNr 14_virtual_mem_part2_mmio_remap/src/_arch/aarch64/memory/mmu/translati Address::new(self as *const _ as usize) } } -@@ -269,7 +268,7 @@ +@@ -273,7 +272,7 @@ /// Create an instance. #[allow(clippy::assertions_on_constants)] @@ -889,7 +889,7 @@ diff -uNr 14_virtual_mem_part2_mmio_remap/src/_arch/aarch64/memory/mmu/translati assert!(bsp::memory::mmu::KernelGranule::SIZE == Granule64KiB::SIZE); // Can't have a zero-sized address space. -@@ -278,11 +277,20 @@ +@@ -282,11 +281,20 @@ Self { lvl3: [[PageDescriptor::new_zeroed(); 8192]; NUM_TABLES], lvl2: [TableDescriptor::new_zeroed(); NUM_TABLES], @@ -912,7 +912,7 @@ diff -uNr 14_virtual_mem_part2_mmio_remap/src/_arch/aarch64/memory/mmu/translati /// The start address of the table's MMIO range. #[inline(always)] fn mmio_start_addr(&self) -> Address { -@@ -338,24 +346,26 @@ +@@ -342,24 +350,26 @@ impl memory::mmu::translation_table::interface::TranslationTable for FixedSizeTranslationTable { @@ -958,8 +958,8 @@ diff -uNr 14_virtual_mem_part2_mmio_remap/src/_arch/aarch64/memory/mmu.rs 15_vir + memory::{mmu::TranslationGranule, Address, Physical, Virtual}, }; use core::intrinsics::unlikely; - use cortex_a::{barrier, regs::*}; -@@ -108,7 +108,7 @@ + use cortex_a::{asm::barrier, registers::*}; +@@ -109,7 +109,7 @@ //------------------------------------------------------------------------------ // OS Interface Code //------------------------------------------------------------------------------ @@ -968,7 +968,7 @@ diff -uNr 14_virtual_mem_part2_mmio_remap/src/_arch/aarch64/memory/mmu.rs 15_vir impl memory::mmu::interface::MMU for MemoryManagementUnit { unsafe fn enable_mmu_and_caching( -@@ -152,4 +152,31 @@ +@@ -153,4 +153,31 @@ fn is_enabled(&self) -> bool { SCTLR_EL1.matches_all(SCTLR_EL1::M::Enable) } diff --git a/16_virtual_mem_part4_higher_half_kernel/README.md b/16_virtual_mem_part4_higher_half_kernel/README.md index 0a438184..fa594703 100644 --- a/16_virtual_mem_part4_higher_half_kernel/README.md +++ b/16_virtual_mem_part4_higher_half_kernel/README.md @@ -246,7 +246,7 @@ diff -uNr 15_virtual_mem_part3_precomputed_tables/Cargo.toml 16_virtual_mem_part diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/cpu/boot.rs 16_virtual_mem_part4_higher_half_kernel/src/_arch/aarch64/cpu/boot.rs --- 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/cpu/boot.rs +++ 16_virtual_mem_part4_higher_half_kernel/src/_arch/aarch64/cpu/boot.rs -@@ -29,7 +29,10 @@ +@@ -30,7 +30,10 @@ /// - The `bss` section is not initialized yet. The code must not use or reference it in any way. /// - The HW state of EL1 must be prepared in a sound way. #[inline(always)] @@ -258,7 +258,7 @@ diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/cpu/boot.rs // Enable timer counter registers for EL1. CNTHCTL_EL2.write(CNTHCTL_EL2::EL1PCEN::SET + CNTHCTL_EL2::EL1PCTEN::SET); -@@ -52,11 +55,11 @@ +@@ -53,11 +56,11 @@ ); // Second, let the link register point to kernel_init(). @@ -272,7 +272,7 @@ diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/cpu/boot.rs } //-------------------------------------------------------------------------------------------------- -@@ -73,9 +76,13 @@ +@@ -74,9 +77,13 @@ #[no_mangle] pub unsafe extern "C" fn _start_rust( phys_kernel_tables_base_addr: u64, @@ -288,7 +288,7 @@ diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/cpu/boot.rs // Turn on the MMU for EL1. let addr = Address::new(phys_kernel_tables_base_addr as usize); -@@ -83,6 +90,7 @@ +@@ -84,6 +91,7 @@ cpu::wait_forever(); } @@ -352,7 +352,7 @@ diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/cpu/boot.s 1 diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/memory/mmu/translation_table.rs 16_virtual_mem_part4_higher_half_kernel/src/_arch/aarch64/memory/mmu/translation_table.rs --- 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/memory/mmu/translation_table.rs +++ 16_virtual_mem_part4_higher_half_kernel/src/_arch/aarch64/memory/mmu/translation_table.rs -@@ -131,7 +131,7 @@ +@@ -135,7 +135,7 @@ /// aligned, so the lvl3 is put first. #[repr(C)] #[repr(align(65536))] @@ -361,7 +361,7 @@ diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/memory/mmu/t /// Page descriptors, covering 64 KiB windows per entry. lvl3: [[PageDescriptor; 8192]; NUM_TABLES], -@@ -258,14 +258,23 @@ +@@ -262,14 +262,23 @@ where [u8; Self::SIZE >> Granule512MiB::SHIFT]: Sized, { @@ -387,7 +387,7 @@ diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/memory/mmu/t /// Create an instance. #[allow(clippy::assertions_on_constants)] const fn _new(for_precompute: bool) -> Self { -@@ -294,20 +303,32 @@ +@@ -298,20 +307,32 @@ /// The start address of the table's MMIO range. #[inline(always)] fn mmio_start_addr(&self) -> Address { @@ -424,7 +424,7 @@ diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/memory/mmu/t } /// Helper to calculate the lvl2 and lvl3 indices from an address. -@@ -316,7 +337,12 @@ +@@ -320,7 +341,12 @@ &self, addr: *const Page, ) -> Result<(usize, usize), &'static str> { @@ -438,7 +438,7 @@ diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/memory/mmu/t let lvl2_index = addr >> Granule512MiB::SHIFT; let lvl3_index = (addr & Granule512MiB::MASK) >> Granule64KiB::SHIFT; -@@ -343,8 +369,9 @@ +@@ -347,8 +373,9 @@ // OS Interface Code //------------------------------------------------------------------------------ @@ -450,7 +450,7 @@ diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/memory/mmu/t { fn init(&mut self) -> Result<(), &'static str> { if self.initialized { -@@ -419,12 +446,16 @@ +@@ -423,12 +450,16 @@ return Err("Not enough MMIO space left"); } @@ -468,7 +468,7 @@ diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/memory/mmu/t Ok(PageSliceDescriptor::from_addr(addr, num_pages)) } -@@ -447,7 +478,7 @@ +@@ -451,7 +482,7 @@ //-------------------------------------------------------------------------------------------------- #[cfg(test)] @@ -481,7 +481,7 @@ diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/memory/mmu/t diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/memory/mmu.rs 16_virtual_mem_part4_higher_half_kernel/src/_arch/aarch64/memory/mmu.rs --- 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/memory/mmu.rs +++ 16_virtual_mem_part4_higher_half_kernel/src/_arch/aarch64/memory/mmu.rs -@@ -65,6 +65,7 @@ +@@ -66,6 +66,7 @@ impl MemoryManagementUnit { /// Setup function for the MAIR_EL1 register. @@ -489,7 +489,7 @@ diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/memory/mmu.r fn set_up_mair(&self) { // Define the memory types being mapped. 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