Switch to tock-registers: Documentation and misc updates

pull/116/head
Andre Richter 3 years ago committed by Andre Richter
parent e1728636c1
commit b23c4318f2

@ -40,14 +40,15 @@ diff -uNr 01_wait_forever/Cargo.toml 02_runtime_init/Cargo.toml
authors = ["Andre Richter <andre.o.richter@gmail.com>"] authors = ["Andre Richter <andre.o.richter@gmail.com>"]
edition = "2018" edition = "2018"
@@ -21,3 +21,7 @@ @@ -21,3 +21,8 @@
##-------------------------------------------------------------------------------------------------- ##--------------------------------------------------------------------------------------------------
[dependencies] [dependencies]
+ +
+# Platform specific dependencies +# Platform specific dependencies
+[target.'cfg(target_arch = "aarch64")'.dependencies] +[target.'cfg(target_arch = "aarch64")'.dependencies]
+cortex-a = { version = "5.x.x" } +cortex-a = { version = "6.x.x" }
+
diff -uNr 01_wait_forever/Makefile 02_runtime_init/Makefile diff -uNr 01_wait_forever/Makefile 02_runtime_init/Makefile
--- 01_wait_forever/Makefile --- 01_wait_forever/Makefile

@ -126,8 +126,8 @@ diff -uNr 04_safe_globals/Cargo.toml 05_drivers_gpio_uart/Cargo.toml
default = [] default = []
-bsp_rpi3 = [] -bsp_rpi3 = []
-bsp_rpi4 = [] -bsp_rpi4 = []
+bsp_rpi3 = ["register"] +bsp_rpi3 = ["tock-registers"]
+bsp_rpi4 = ["register"] +bsp_rpi4 = ["tock-registers"]
[[bin]] [[bin]]
name = "kernel" name = "kernel"
@ -136,11 +136,11 @@ diff -uNr 04_safe_globals/Cargo.toml 05_drivers_gpio_uart/Cargo.toml
[dependencies] [dependencies]
+# Optional dependencies +# Optional dependencies
+register = { version = "1.x.x", optional = true } +tock-registers = { version = "0.7.x", default-features = false, features = ["register_types"], optional = true }
+ +
# Platform specific dependencies # Platform specific dependencies
[target.'cfg(target_arch = "aarch64")'.dependencies] [target.'cfg(target_arch = "aarch64")'.dependencies]
cortex-a = { version = "5.x.x" } cortex-a = { version = "6.x.x" }
diff -uNr 04_safe_globals/Makefile 05_drivers_gpio_uart/Makefile diff -uNr 04_safe_globals/Makefile 05_drivers_gpio_uart/Makefile
--- 04_safe_globals/Makefile --- 04_safe_globals/Makefile
@ -220,7 +220,7 @@ diff -uNr 04_safe_globals/src/_arch/aarch64/cpu.rs 05_drivers_gpio_uart/src/_arc
diff -uNr 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs diff -uNr 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
--- 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs --- 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
+++ 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs +++ 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
@@ -0,0 +1,221 @@ @@ -0,0 +1,225 @@
+// SPDX-License-Identifier: MIT OR Apache-2.0 +// SPDX-License-Identifier: MIT OR Apache-2.0
+// +//
+// Copyright (c) 2018-2021 Andre Richter <andre.o.richter@gmail.com> +// Copyright (c) 2018-2021 Andre Richter <andre.o.richter@gmail.com>
@ -231,7 +231,11 @@ diff -uNr 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 05_drivers_g
+ bsp::device_driver::common::MMIODerefWrapper, driver, synchronization, + bsp::device_driver::common::MMIODerefWrapper, driver, synchronization,
+ synchronization::NullLock, + synchronization::NullLock,
+}; +};
+use register::{mmio::*, register_bitfields, register_structs}; +use tock_registers::{
+ interfaces::{ReadWriteable, Writeable},
+ register_bitfields, register_structs,
+ registers::ReadWrite,
+};
+ +
+//-------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------
+// Private Definitions +// Private Definitions
@ -446,7 +450,7 @@ diff -uNr 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 05_drivers_g
diff -uNr 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs diff -uNr 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
--- 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs --- 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
+++ 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs +++ 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
@@ -0,0 +1,403 @@ @@ -0,0 +1,408 @@
+// SPDX-License-Identifier: MIT OR Apache-2.0 +// SPDX-License-Identifier: MIT OR Apache-2.0
+// +//
+// Copyright (c) 2018-2021 Andre Richter <andre.o.richter@gmail.com> +// Copyright (c) 2018-2021 Andre Richter <andre.o.richter@gmail.com>
@ -463,7 +467,11 @@ diff -uNr 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 05_dri
+ synchronization::NullLock, + synchronization::NullLock,
+}; +};
+use core::fmt; +use core::fmt;
+use register::{mmio::*, register_bitfields, register_structs}; +use tock_registers::{
+ interfaces::{Readable, Writeable},
+ register_bitfields, register_structs,
+ registers::{ReadOnly, ReadWrite, WriteOnly},
+};
+ +
+//-------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------
+// Private Definitions +// Private Definitions
@ -530,6 +538,7 @@ diff -uNr 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 05_dri
+ LCR_H [ + LCR_H [
+ /// Word length. These bits indicate the number of data bits transmitted or received in a + /// Word length. These bits indicate the number of data bits transmitted or received in a
+ /// frame. + /// frame.
+ #[allow(clippy::enum_variant_names)]
+ WLEN OFFSET(5) NUMBITS(2) [ + WLEN OFFSET(5) NUMBITS(2) [
+ FiveBit = 0b00, + FiveBit = 0b00,
+ SixBit = 0b01, + SixBit = 0b01,

@ -279,7 +279,7 @@ diff -uNr 05_drivers_gpio_uart/src/_arch/aarch64/cpu/boot.s 06_uart_chainloader/
diff -uNr 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs diff -uNr 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
--- 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs --- 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
+++ 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs +++ 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
@@ -144,7 +144,7 @@ @@ -148,7 +148,7 @@
// Make an educated guess for a good delay value (Sequence described in the BCM2837 // Make an educated guess for a good delay value (Sequence described in the BCM2837
// peripherals PDF). // peripherals PDF).
// //
@ -292,7 +292,7 @@ diff -uNr 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 06_uart
diff -uNr 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs diff -uNr 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
--- 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs --- 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
+++ 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs +++ 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
@@ -279,7 +279,7 @@ @@ -284,7 +284,7 @@
} }
/// Retrieve a character. /// Retrieve a character.
@ -301,7 +301,7 @@ diff -uNr 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 0
// If RX FIFO is empty, // If RX FIFO is empty,
if self.registers.FR.matches_all(FR::RXFE::SET) { if self.registers.FR.matches_all(FR::RXFE::SET) {
// immediately return in non-blocking mode. // immediately return in non-blocking mode.
@@ -294,12 +294,7 @@ @@ -299,12 +299,7 @@
} }
// Read one character. // Read one character.
@ -315,7 +315,7 @@ diff -uNr 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 0
// Update statistics. // Update statistics.
self.chars_read += 1; self.chars_read += 1;
@@ -379,14 +374,14 @@ @@ -384,14 +379,14 @@
impl console::interface::Read for PL011Uart { impl console::interface::Read for PL011Uart {
fn read_char(&self) -> char { fn read_char(&self) -> char {
self.inner self.inner

@ -221,7 +221,7 @@ diff -uNr 06_uart_chainloader/src/_arch/aarch64/cpu.rs 07_timestamps/src/_arch/a
diff -uNr 06_uart_chainloader/src/_arch/aarch64/time.rs 07_timestamps/src/_arch/aarch64/time.rs diff -uNr 06_uart_chainloader/src/_arch/aarch64/time.rs 07_timestamps/src/_arch/aarch64/time.rs
--- 06_uart_chainloader/src/_arch/aarch64/time.rs --- 06_uart_chainloader/src/_arch/aarch64/time.rs
+++ 07_timestamps/src/_arch/aarch64/time.rs +++ 07_timestamps/src/_arch/aarch64/time.rs
@@ -0,0 +1,118 @@ @@ -0,0 +1,119 @@
+// SPDX-License-Identifier: MIT OR Apache-2.0 +// SPDX-License-Identifier: MIT OR Apache-2.0
+// +//
+// Copyright (c) 2018-2021 Andre Richter <andre.o.richter@gmail.com> +// Copyright (c) 2018-2021 Andre Richter <andre.o.richter@gmail.com>
@ -237,7 +237,8 @@ diff -uNr 06_uart_chainloader/src/_arch/aarch64/time.rs 07_timestamps/src/_arch/
+ +
+use crate::{time, warn}; +use crate::{time, warn};
+use core::time::Duration; +use core::time::Duration;
+use cortex_a::{barrier, regs::*}; +use cortex_a::{asm::barrier, registers::*};
+use tock_registers::interfaces::{ReadWriteable, Readable, Writeable};
+ +
+//-------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------
+// Private Definitions +// Private Definitions
@ -344,7 +345,7 @@ diff -uNr 06_uart_chainloader/src/_arch/aarch64/time.rs 07_timestamps/src/_arch/
diff -uNr 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 07_timestamps/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs diff -uNr 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 07_timestamps/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
--- 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs --- 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
+++ 07_timestamps/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs +++ 07_timestamps/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
@@ -139,25 +139,19 @@ @@ -143,25 +143,19 @@
/// Disable pull-up/down on pins 14 and 15. /// Disable pull-up/down on pins 14 and 15.
#[cfg(feature = "bsp_rpi3")] #[cfg(feature = "bsp_rpi3")]
fn disable_pud_14_15_bcm2837(&mut self) { fn disable_pud_14_15_bcm2837(&mut self) {
@ -380,7 +381,7 @@ diff -uNr 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 07_times
diff -uNr 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 07_timestamps/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs diff -uNr 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 07_timestamps/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
--- 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs --- 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
+++ 07_timestamps/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs +++ 07_timestamps/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
@@ -279,7 +279,7 @@ @@ -284,7 +284,7 @@
} }
/// Retrieve a character. /// Retrieve a character.
@ -389,7 +390,7 @@ diff -uNr 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 07
// If RX FIFO is empty, // If RX FIFO is empty,
if self.registers.FR.matches_all(FR::RXFE::SET) { if self.registers.FR.matches_all(FR::RXFE::SET) {
// immediately return in non-blocking mode. // immediately return in non-blocking mode.
@@ -294,7 +294,12 @@ @@ -299,7 +299,12 @@
} }
// Read one character. // Read one character.
@ -403,7 +404,7 @@ diff -uNr 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 07
// Update statistics. // Update statistics.
self.chars_read += 1; self.chars_read += 1;
@@ -374,14 +379,14 @@ @@ -379,14 +384,14 @@
impl console::interface::Read for PL011Uart { impl console::interface::Read for PL011Uart {
fn read_char(&self) -> char { fn read_char(&self) -> char {
self.inner self.inner

@ -211,11 +211,12 @@ diff -uNr 08_hw_debug_JTAG/Cargo.toml 09_privilege_level/Cargo.toml
diff -uNr 08_hw_debug_JTAG/src/_arch/aarch64/cpu/boot.rs 09_privilege_level/src/_arch/aarch64/cpu/boot.rs diff -uNr 08_hw_debug_JTAG/src/_arch/aarch64/cpu/boot.rs 09_privilege_level/src/_arch/aarch64/cpu/boot.rs
--- 08_hw_debug_JTAG/src/_arch/aarch64/cpu/boot.rs --- 08_hw_debug_JTAG/src/_arch/aarch64/cpu/boot.rs
+++ 09_privilege_level/src/_arch/aarch64/cpu/boot.rs +++ 09_privilege_level/src/_arch/aarch64/cpu/boot.rs
@@ -11,17 +11,67 @@ @@ -11,17 +11,68 @@
//! //!
//! crate::cpu::boot::arch_boot //! crate::cpu::boot::arch_boot
+use cortex_a::{asm, regs::*}; +use cortex_a::{asm, registers::*};
+use tock_registers::interfaces::Writeable;
+ +
// Assembly counterpart to this file. // Assembly counterpart to this file.
global_asm!(include_str!("boot.s")); global_asm!(include_str!("boot.s"));
@ -323,7 +324,7 @@ diff -uNr 08_hw_debug_JTAG/src/_arch/aarch64/cpu/boot.s 09_privilege_level/src/_
diff -uNr 08_hw_debug_JTAG/src/_arch/aarch64/exception/asynchronous.rs 09_privilege_level/src/_arch/aarch64/exception/asynchronous.rs diff -uNr 08_hw_debug_JTAG/src/_arch/aarch64/exception/asynchronous.rs 09_privilege_level/src/_arch/aarch64/exception/asynchronous.rs
--- 08_hw_debug_JTAG/src/_arch/aarch64/exception/asynchronous.rs --- 08_hw_debug_JTAG/src/_arch/aarch64/exception/asynchronous.rs
+++ 09_privilege_level/src/_arch/aarch64/exception/asynchronous.rs +++ 09_privilege_level/src/_arch/aarch64/exception/asynchronous.rs
@@ -0,0 +1,81 @@ @@ -0,0 +1,82 @@
+// SPDX-License-Identifier: MIT OR Apache-2.0 +// SPDX-License-Identifier: MIT OR Apache-2.0
+// +//
+// Copyright (c) 2018-2021 Andre Richter <andre.o.richter@gmail.com> +// Copyright (c) 2018-2021 Andre Richter <andre.o.richter@gmail.com>
@ -337,14 +338,15 @@ diff -uNr 08_hw_debug_JTAG/src/_arch/aarch64/exception/asynchronous.rs 09_privil
+//! +//!
+//! crate::exception::asynchronous::arch_asynchronous +//! crate::exception::asynchronous::arch_asynchronous
+ +
+use cortex_a::regs::*; +use cortex_a::registers::*;
+use tock_registers::interfaces::Readable;
+ +
+//-------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------
+// Private Definitions +// Private Definitions
+//-------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------
+ +
+trait DaifField { +trait DaifField {
+ fn daif_field() -> register::Field<u64, DAIF::Register>; + fn daif_field() -> tock_registers::fields::Field<u64, DAIF::Register>;
+} +}
+ +
+struct Debug; +struct Debug;
@ -357,25 +359,25 @@ diff -uNr 08_hw_debug_JTAG/src/_arch/aarch64/exception/asynchronous.rs 09_privil
+//-------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------
+ +
+impl DaifField for Debug { +impl DaifField for Debug {
+ fn daif_field() -> register::Field<u64, DAIF::Register> { + fn daif_field() -> tock_registers::fields::Field<u64, DAIF::Register> {
+ DAIF::D + DAIF::D
+ } + }
+} +}
+ +
+impl DaifField for SError { +impl DaifField for SError {
+ fn daif_field() -> register::Field<u64, DAIF::Register> { + fn daif_field() -> tock_registers::fields::Field<u64, DAIF::Register> {
+ DAIF::A + DAIF::A
+ } + }
+} +}
+ +
+impl DaifField for IRQ { +impl DaifField for IRQ {
+ fn daif_field() -> register::Field<u64, DAIF::Register> { + fn daif_field() -> tock_registers::fields::Field<u64, DAIF::Register> {
+ DAIF::I + DAIF::I
+ } + }
+} +}
+ +
+impl DaifField for FIQ { +impl DaifField for FIQ {
+ fn daif_field() -> register::Field<u64, DAIF::Register> { + fn daif_field() -> tock_registers::fields::Field<u64, DAIF::Register> {
+ DAIF::F + DAIF::F
+ } + }
+} +}
@ -409,7 +411,7 @@ diff -uNr 08_hw_debug_JTAG/src/_arch/aarch64/exception/asynchronous.rs 09_privil
diff -uNr 08_hw_debug_JTAG/src/_arch/aarch64/exception.rs 09_privilege_level/src/_arch/aarch64/exception.rs diff -uNr 08_hw_debug_JTAG/src/_arch/aarch64/exception.rs 09_privilege_level/src/_arch/aarch64/exception.rs
--- 08_hw_debug_JTAG/src/_arch/aarch64/exception.rs --- 08_hw_debug_JTAG/src/_arch/aarch64/exception.rs
+++ 09_privilege_level/src/_arch/aarch64/exception.rs +++ 09_privilege_level/src/_arch/aarch64/exception.rs
@@ -0,0 +1,30 @@ @@ -0,0 +1,31 @@
+// SPDX-License-Identifier: MIT OR Apache-2.0 +// SPDX-License-Identifier: MIT OR Apache-2.0
+// +//
+// Copyright (c) 2018-2021 Andre Richter <andre.o.richter@gmail.com> +// Copyright (c) 2018-2021 Andre Richter <andre.o.richter@gmail.com>
@ -423,7 +425,8 @@ diff -uNr 08_hw_debug_JTAG/src/_arch/aarch64/exception.rs 09_privilege_level/src
+//! +//!
+//! crate::exception::arch_exception +//! crate::exception::arch_exception
+ +
+use cortex_a::regs::*; +use cortex_a::registers::*;
+use tock_registers::interfaces::Readable;
+ +
+//-------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------
+// Public Code +// Public Code

@ -364,7 +364,7 @@ diff -uNr 09_privilege_level/Cargo.toml 10_virtual_mem_part1_identity_mapping/Ca
diff -uNr 09_privilege_level/src/_arch/aarch64/memory/mmu/translation_table.rs 10_virtual_mem_part1_identity_mapping/src/_arch/aarch64/memory/mmu/translation_table.rs diff -uNr 09_privilege_level/src/_arch/aarch64/memory/mmu/translation_table.rs 10_virtual_mem_part1_identity_mapping/src/_arch/aarch64/memory/mmu/translation_table.rs
--- 09_privilege_level/src/_arch/aarch64/memory/mmu/translation_table.rs --- 09_privilege_level/src/_arch/aarch64/memory/mmu/translation_table.rs
+++ 10_virtual_mem_part1_identity_mapping/src/_arch/aarch64/memory/mmu/translation_table.rs +++ 10_virtual_mem_part1_identity_mapping/src/_arch/aarch64/memory/mmu/translation_table.rs
@@ -0,0 +1,288 @@ @@ -0,0 +1,292 @@
+// SPDX-License-Identifier: MIT OR Apache-2.0 +// SPDX-License-Identifier: MIT OR Apache-2.0
+// +//
+// Copyright (c) 2021 Andre Richter <andre.o.richter@gmail.com> +// Copyright (c) 2021 Andre Richter <andre.o.richter@gmail.com>
@ -388,7 +388,11 @@ diff -uNr 09_privilege_level/src/_arch/aarch64/memory/mmu/translation_table.rs 1
+ }, + },
+}; +};
+use core::convert; +use core::convert;
+use register::{register_bitfields, InMemoryRegister}; +use tock_registers::{
+ interfaces::{Readable, Writeable},
+ register_bitfields,
+ registers::InMemoryRegister,
+};
+ +
+//-------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------
+// Private Definitions +// Private Definitions
@ -549,7 +553,7 @@ diff -uNr 09_privilege_level/src/_arch/aarch64/memory/mmu/translation_table.rs 1
+ +
+/// Convert the kernel's generic memory attributes to HW-specific attributes of the MMU. +/// Convert the kernel's generic memory attributes to HW-specific attributes of the MMU.
+impl convert::From<AttributeFields> +impl convert::From<AttributeFields>
+ for register::FieldValue<u64, STAGE1_PAGE_DESCRIPTOR::Register> + for tock_registers::fields::FieldValue<u64, STAGE1_PAGE_DESCRIPTOR::Register>
+{ +{
+ fn from(attribute_fields: AttributeFields) -> Self { + fn from(attribute_fields: AttributeFields) -> Self {
+ // Memory attributes. + // Memory attributes.
@ -657,7 +661,7 @@ diff -uNr 09_privilege_level/src/_arch/aarch64/memory/mmu/translation_table.rs 1
diff -uNr 09_privilege_level/src/_arch/aarch64/memory/mmu.rs 10_virtual_mem_part1_identity_mapping/src/_arch/aarch64/memory/mmu.rs diff -uNr 09_privilege_level/src/_arch/aarch64/memory/mmu.rs 10_virtual_mem_part1_identity_mapping/src/_arch/aarch64/memory/mmu.rs
--- 09_privilege_level/src/_arch/aarch64/memory/mmu.rs --- 09_privilege_level/src/_arch/aarch64/memory/mmu.rs
+++ 10_virtual_mem_part1_identity_mapping/src/_arch/aarch64/memory/mmu.rs +++ 10_virtual_mem_part1_identity_mapping/src/_arch/aarch64/memory/mmu.rs
@@ -0,0 +1,164 @@ @@ -0,0 +1,165 @@
+// SPDX-License-Identifier: MIT OR Apache-2.0 +// SPDX-License-Identifier: MIT OR Apache-2.0
+// +//
+// Copyright (c) 2018-2021 Andre Richter <andre.o.richter@gmail.com> +// Copyright (c) 2018-2021 Andre Richter <andre.o.richter@gmail.com>
@ -678,7 +682,8 @@ diff -uNr 09_privilege_level/src/_arch/aarch64/memory/mmu.rs 10_virtual_mem_part
+ memory::mmu::{translation_table::KernelTranslationTable, TranslationGranule}, + memory::mmu::{translation_table::KernelTranslationTable, TranslationGranule},
+}; +};
+use core::intrinsics::unlikely; +use core::intrinsics::unlikely;
+use cortex_a::{barrier, regs::*}; +use cortex_a::{asm::barrier, registers::*};
+use tock_registers::interfaces::{ReadWriteable, Readable, Writeable};
+ +
+//-------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------
+// Private Definitions +// Private Definitions

@ -492,14 +492,18 @@ diff -uNr 10_virtual_mem_part1_identity_mapping/Cargo.toml 11_exceptions_part1_g
diff -uNr 10_virtual_mem_part1_identity_mapping/src/_arch/aarch64/exception.rs 11_exceptions_part1_groundwork/src/_arch/aarch64/exception.rs diff -uNr 10_virtual_mem_part1_identity_mapping/src/_arch/aarch64/exception.rs 11_exceptions_part1_groundwork/src/_arch/aarch64/exception.rs
--- 10_virtual_mem_part1_identity_mapping/src/_arch/aarch64/exception.rs --- 10_virtual_mem_part1_identity_mapping/src/_arch/aarch64/exception.rs
+++ 11_exceptions_part1_groundwork/src/_arch/aarch64/exception.rs +++ 11_exceptions_part1_groundwork/src/_arch/aarch64/exception.rs
@@ -11,7 +11,224 @@ @@ -11,8 +11,227 @@
//! //!
//! crate::exception::arch_exception //! crate::exception::arch_exception
-use cortex_a::regs::*; -use cortex_a::registers::*;
-use tock_registers::interfaces::Readable;
+use core::{cell::UnsafeCell, fmt}; +use core::{cell::UnsafeCell, fmt};
+use cortex_a::{asm, barrier, regs::*}; +use cortex_a::{asm, asm::barrier, registers::*};
+use register::InMemoryRegister; +use tock_registers::{
+ interfaces::{Readable, Writeable},
+ registers::InMemoryRegister,
+};
+ +
+// Assembly counterpart to this file. +// Assembly counterpart to this file.
+global_asm!(include_str!("exception.s")); +global_asm!(include_str!("exception.s"));
@ -718,7 +722,7 @@ diff -uNr 10_virtual_mem_part1_identity_mapping/src/_arch/aarch64/exception.rs 1
//-------------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------------
// Public Code // Public Code
@@ -28,3 +245,23 @@ @@ -29,3 +248,23 @@
_ => (PrivilegeLevel::Unknown, "Unknown"), _ => (PrivilegeLevel::Unknown, "Unknown"),
} }
} }

@ -825,10 +825,10 @@ diff -uNr 11_exceptions_part1_groundwork/Cargo.toml 12_integrated_testing/Cargo.
authors = ["Andre Richter <andre.o.richter@gmail.com>"] authors = ["Andre Richter <andre.o.richter@gmail.com>"]
edition = "2018" edition = "2018"
@@ -11,20 +11,46 @@ @@ -11,21 +11,46 @@
default = [] default = []
bsp_rpi3 = ["register"] bsp_rpi3 = ["tock-registers"]
bsp_rpi4 = ["register"] bsp_rpi4 = ["tock-registers"]
- -
-[[bin]] -[[bin]]
-name = "kernel" -name = "kernel"
@ -843,14 +843,13 @@ diff -uNr 11_exceptions_part1_groundwork/Cargo.toml 12_integrated_testing/Cargo.
+test-types = { path = "test-types" } +test-types = { path = "test-types" }
# Optional dependencies # Optional dependencies
-register = { version = "1.x.x", optional = true } tock-registers = { version = "0.7.x", default-features = false, features = ["register_types"], optional = true }
+register = { version = "1.x.x", features = ["no_std_unit_tests"], optional = true } +qemu-exit = { version = "2.x.x", optional = true }
+qemu-exit = { version = "1.x.x", optional = true }
# Platform specific dependencies # Platform specific dependencies
[target.'cfg(target_arch = "aarch64")'.dependencies] [target.'cfg(target_arch = "aarch64")'.dependencies]
cortex-a = { version = "5.x.x" } cortex-a = { version = "6.x.x" }
+
+##-------------------------------------------------------------------------------------------------- +##--------------------------------------------------------------------------------------------------
+## Testing +## Testing
+##-------------------------------------------------------------------------------------------------- +##--------------------------------------------------------------------------------------------------
@ -1010,12 +1009,12 @@ diff -uNr 11_exceptions_part1_groundwork/src/_arch/aarch64/exception.rs 12_integ
//! crate::exception::arch_exception //! crate::exception::arch_exception
use core::{cell::UnsafeCell, fmt}; use core::{cell::UnsafeCell, fmt};
-use cortex_a::{asm, barrier, regs::*}; -use cortex_a::{asm, asm::barrier, registers::*};
+use cortex_a::{barrier, regs::*}; +use cortex_a::{asm::barrier, registers::*};
use register::InMemoryRegister; use tock_registers::{
interfaces::{Readable, Writeable},
// Assembly counterpart to this file. registers::InMemoryRegister,
@@ -87,16 +87,6 @@ @@ -90,16 +90,6 @@
#[no_mangle] #[no_mangle]
unsafe extern "C" fn current_elx_synchronous(e: &mut ExceptionContext) { unsafe extern "C" fn current_elx_synchronous(e: &mut ExceptionContext) {
@ -1036,7 +1035,7 @@ diff -uNr 11_exceptions_part1_groundwork/src/_arch/aarch64/exception.rs 12_integ
diff -uNr 11_exceptions_part1_groundwork/src/_arch/aarch64/memory/mmu/translation_table.rs 12_integrated_testing/src/_arch/aarch64/memory/mmu/translation_table.rs diff -uNr 11_exceptions_part1_groundwork/src/_arch/aarch64/memory/mmu/translation_table.rs 12_integrated_testing/src/_arch/aarch64/memory/mmu/translation_table.rs
--- 11_exceptions_part1_groundwork/src/_arch/aarch64/memory/mmu/translation_table.rs --- 11_exceptions_part1_groundwork/src/_arch/aarch64/memory/mmu/translation_table.rs
+++ 12_integrated_testing/src/_arch/aarch64/memory/mmu/translation_table.rs +++ 12_integrated_testing/src/_arch/aarch64/memory/mmu/translation_table.rs
@@ -286,3 +286,31 @@ @@ -290,3 +290,31 @@
self.lvl2.phys_start_addr_u64() self.lvl2.phys_start_addr_u64()
} }
} }
@ -1072,7 +1071,7 @@ diff -uNr 11_exceptions_part1_groundwork/src/_arch/aarch64/memory/mmu/translatio
diff -uNr 11_exceptions_part1_groundwork/src/_arch/aarch64/memory/mmu.rs 12_integrated_testing/src/_arch/aarch64/memory/mmu.rs diff -uNr 11_exceptions_part1_groundwork/src/_arch/aarch64/memory/mmu.rs 12_integrated_testing/src/_arch/aarch64/memory/mmu.rs
--- 11_exceptions_part1_groundwork/src/_arch/aarch64/memory/mmu.rs --- 11_exceptions_part1_groundwork/src/_arch/aarch64/memory/mmu.rs
+++ 12_integrated_testing/src/_arch/aarch64/memory/mmu.rs +++ 12_integrated_testing/src/_arch/aarch64/memory/mmu.rs
@@ -162,3 +162,33 @@ @@ -163,3 +163,33 @@
SCTLR_EL1.matches_all(SCTLR_EL1::M::Enable) SCTLR_EL1.matches_all(SCTLR_EL1::M::Enable)
} }
} }

@ -761,7 +761,7 @@ diff -uNr 12_integrated_testing/Cargo.toml 13_exceptions_part2_peripheral_IRQs/C
diff -uNr 12_integrated_testing/src/_arch/aarch64/cpu/smp.rs 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/cpu/smp.rs diff -uNr 12_integrated_testing/src/_arch/aarch64/cpu/smp.rs 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/cpu/smp.rs
--- 12_integrated_testing/src/_arch/aarch64/cpu/smp.rs --- 12_integrated_testing/src/_arch/aarch64/cpu/smp.rs
+++ 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/cpu/smp.rs +++ 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/cpu/smp.rs
@@ -0,0 +1,29 @@ @@ -0,0 +1,30 @@
+// SPDX-License-Identifier: MIT OR Apache-2.0 +// SPDX-License-Identifier: MIT OR Apache-2.0
+// +//
+// Copyright (c) 2018-2021 Andre Richter <andre.o.richter@gmail.com> +// Copyright (c) 2018-2021 Andre Richter <andre.o.richter@gmail.com>
@ -775,7 +775,8 @@ diff -uNr 12_integrated_testing/src/_arch/aarch64/cpu/smp.rs 13_exceptions_part2
+//! +//!
+//! crate::cpu::smp::arch_smp +//! crate::cpu::smp::arch_smp
+ +
+use cortex_a::regs::*; +use cortex_a::registers::*;
+use tock_registers::interfaces::Readable;
+ +
+//-------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------
+// Public Code +// Public Code
@ -795,7 +796,14 @@ diff -uNr 12_integrated_testing/src/_arch/aarch64/cpu/smp.rs 13_exceptions_part2
diff -uNr 12_integrated_testing/src/_arch/aarch64/exception/asynchronous.rs 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/exception/asynchronous.rs diff -uNr 12_integrated_testing/src/_arch/aarch64/exception/asynchronous.rs 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/exception/asynchronous.rs
--- 12_integrated_testing/src/_arch/aarch64/exception/asynchronous.rs --- 12_integrated_testing/src/_arch/aarch64/exception/asynchronous.rs
+++ 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/exception/asynchronous.rs +++ 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/exception/asynchronous.rs
@@ -17,6 +17,10 @@ @@ -12,12 +12,16 @@
//! crate::exception::asynchronous::arch_asynchronous
use cortex_a::registers::*;
-use tock_registers::interfaces::Readable;
+use tock_registers::interfaces::{Readable, Writeable};
//--------------------------------------------------------------------------------------------------
// Private Definitions // Private Definitions
//-------------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------------
@ -804,9 +812,9 @@ diff -uNr 12_integrated_testing/src/_arch/aarch64/exception/asynchronous.rs 13_e
+} +}
+ +
trait DaifField { trait DaifField {
fn daif_field() -> register::Field<u64, DAIF::Register>; fn daif_field() -> tock_registers::fields::Field<u64, DAIF::Register>;
} }
@@ -65,6 +69,71 @@ @@ -66,6 +70,71 @@
// Public Code // Public Code
//-------------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------------
@ -888,9 +896,9 @@ diff -uNr 12_integrated_testing/src/_arch/aarch64/exception.rs 13_exceptions_par
+use crate::{bsp, exception}; +use crate::{bsp, exception};
use core::{cell::UnsafeCell, fmt}; use core::{cell::UnsafeCell, fmt};
use cortex_a::{barrier, regs::*}; use cortex_a::{asm::barrier, registers::*};
use register::InMemoryRegister; use tock_registers::{
@@ -91,8 +92,11 @@ @@ -94,8 +95,11 @@
} }
#[no_mangle] #[no_mangle]
@ -908,7 +916,7 @@ diff -uNr 12_integrated_testing/src/_arch/aarch64/exception.rs 13_exceptions_par
diff -uNr 12_integrated_testing/src/bsp/device_driver/arm/gicv2/gicc.rs 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gicc.rs diff -uNr 12_integrated_testing/src/bsp/device_driver/arm/gicv2/gicc.rs 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gicc.rs
--- 12_integrated_testing/src/bsp/device_driver/arm/gicv2/gicc.rs --- 12_integrated_testing/src/bsp/device_driver/arm/gicv2/gicc.rs
+++ 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gicc.rs +++ 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gicc.rs
@@ -0,0 +1,137 @@ @@ -0,0 +1,141 @@
+// SPDX-License-Identifier: MIT OR Apache-2.0 +// SPDX-License-Identifier: MIT OR Apache-2.0
+// +//
+// Copyright (c) 2020-2021 Andre Richter <andre.o.richter@gmail.com> +// Copyright (c) 2020-2021 Andre Richter <andre.o.richter@gmail.com>
@ -916,7 +924,11 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/arm/gicv2/gicc.rs 13_excep
+//! GICC Driver - GIC CPU interface. +//! GICC Driver - GIC CPU interface.
+ +
+use crate::{bsp::device_driver::common::MMIODerefWrapper, exception}; +use crate::{bsp::device_driver::common::MMIODerefWrapper, exception};
+use register::{mmio::*, register_bitfields, register_structs}; +use tock_registers::{
+ interfaces::{Readable, Writeable},
+ register_bitfields, register_structs,
+ registers::ReadWrite,
+};
+ +
+//-------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------
+// Private Definitions +// Private Definitions
@ -1050,7 +1062,7 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/arm/gicv2/gicc.rs 13_excep
diff -uNr 12_integrated_testing/src/bsp/device_driver/arm/gicv2/gicd.rs 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gicd.rs diff -uNr 12_integrated_testing/src/bsp/device_driver/arm/gicv2/gicd.rs 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gicd.rs
--- 12_integrated_testing/src/bsp/device_driver/arm/gicv2/gicd.rs --- 12_integrated_testing/src/bsp/device_driver/arm/gicv2/gicd.rs
+++ 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gicd.rs +++ 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gicd.rs
@@ -0,0 +1,195 @@ @@ -0,0 +1,199 @@
+// SPDX-License-Identifier: MIT OR Apache-2.0 +// SPDX-License-Identifier: MIT OR Apache-2.0
+// +//
+// Copyright (c) 2020-2021 Andre Richter <andre.o.richter@gmail.com> +// Copyright (c) 2020-2021 Andre Richter <andre.o.richter@gmail.com>
@ -1064,7 +1076,11 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/arm/gicv2/gicd.rs 13_excep
+ bsp::device_driver::common::MMIODerefWrapper, state, synchronization, + bsp::device_driver::common::MMIODerefWrapper, state, synchronization,
+ synchronization::IRQSafeNullLock, + synchronization::IRQSafeNullLock,
+}; +};
+use register::{mmio::*, register_bitfields, register_structs}; +use tock_registers::{
+ interfaces::{Readable, Writeable},
+ register_bitfields, register_structs,
+ registers::{ReadOnly, ReadWrite},
+};
+ +
+//-------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------
+// Private Definitions +// Private Definitions
@ -1495,9 +1511,9 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 13_exc
- synchronization::NullLock, - synchronization::NullLock,
+ synchronization::IRQSafeNullLock, + synchronization::IRQSafeNullLock,
}; };
use register::{mmio::*, register_bitfields, register_structs}; use tock_registers::{
interfaces::{ReadWriteable, Writeable},
@@ -117,7 +117,7 @@ @@ -121,7 +121,7 @@
/// Representation of the GPIO HW. /// Representation of the GPIO HW.
pub struct GPIO { pub struct GPIO {
@ -1506,7 +1522,7 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 13_exc
} }
//-------------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------------
@@ -193,7 +193,7 @@ @@ -197,7 +197,7 @@
/// - The user must ensure to provide a correct MMIO start address. /// - The user must ensure to provide a correct MMIO start address.
pub const unsafe fn new(mmio_start_addr: usize) -> Self { pub const unsafe fn new(mmio_start_addr: usize) -> Self {
Self { Self {
@ -1519,12 +1535,12 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 13_exc
diff -uNr 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_interrupt_controller/peripheral_ic.rs 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_interrupt_controller/peripheral_ic.rs diff -uNr 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_interrupt_controller/peripheral_ic.rs 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_interrupt_controller/peripheral_ic.rs
--- 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_interrupt_controller/peripheral_ic.rs --- 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_interrupt_controller/peripheral_ic.rs
+++ 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_interrupt_controller/peripheral_ic.rs +++ 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_interrupt_controller/peripheral_ic.rs
@@ -0,0 +1,163 @@ @@ -0,0 +1,167 @@
+// SPDX-License-Identifier: MIT OR Apache-2.0 +// SPDX-License-Identifier: MIT OR Apache-2.0
+// +//
+// Copyright (c) 2020-2021 Andre Richter <andre.o.richter@gmail.com> +// Copyright (c) 2020-2021 Andre Richter <andre.o.richter@gmail.com>
+ +
+//! Peripheral Interrupt regsler Driver. +//! Peripheral Interrupt Controller Driver.
+ +
+use super::{InterruptController, PendingIRQs, PeripheralIRQ}; +use super::{InterruptController, PendingIRQs, PeripheralIRQ};
+use crate::{ +use crate::{
@ -1532,7 +1548,11 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_interrupt_cont
+ exception, synchronization, + exception, synchronization,
+ synchronization::{IRQSafeNullLock, InitStateLock}, + synchronization::{IRQSafeNullLock, InitStateLock},
+}; +};
+use register::{mmio::*, register_structs}; +use tock_registers::{
+ interfaces::{Readable, Writeable},
+ register_structs,
+ registers::{ReadOnly, WriteOnly},
+};
+ +
+//-------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------
+// Private Definitions +// Private Definitions
@ -1833,8 +1853,8 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
+ synchronization, synchronization::IRQSafeNullLock, + synchronization, synchronization::IRQSafeNullLock,
}; };
use core::fmt; use core::fmt;
use register::{mmio::*, register_bitfields, register_structs}; use tock_registers::{
@@ -135,6 +135,52 @@ @@ -140,6 +140,52 @@
] ]
], ],
@ -1887,7 +1907,7 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
/// Interrupt Clear Register. /// Interrupt Clear Register.
ICR [ ICR [
/// Meta field for all pending interrupts. /// Meta field for all pending interrupts.
@@ -153,7 +199,10 @@ @@ -158,7 +204,10 @@
(0x28 => FBRD: WriteOnly<u32, FBRD::Register>), (0x28 => FBRD: WriteOnly<u32, FBRD::Register>),
(0x2c => LCR_H: WriteOnly<u32, LCR_H::Register>), (0x2c => LCR_H: WriteOnly<u32, LCR_H::Register>),
(0x30 => CR: WriteOnly<u32, CR::Register>), (0x30 => CR: WriteOnly<u32, CR::Register>),
@ -1899,7 +1919,7 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
(0x44 => ICR: WriteOnly<u32, ICR::Register>), (0x44 => ICR: WriteOnly<u32, ICR::Register>),
(0x48 => @END), (0x48 => @END),
} }
@@ -183,7 +232,8 @@ @@ -188,7 +237,8 @@
/// Representation of the UART. /// Representation of the UART.
pub struct PL011Uart { pub struct PL011Uart {
@ -1909,7 +1929,7 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
} }
//-------------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------------
@@ -251,6 +301,14 @@ @@ -256,6 +306,14 @@
.LCR_H .LCR_H
.write(LCR_H::WLEN::EightBit + LCR_H::FEN::FifosEnabled); .write(LCR_H::WLEN::EightBit + LCR_H::FEN::FifosEnabled);
@ -1924,7 +1944,7 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
// Turn the UART on. // Turn the UART on.
self.registers self.registers
.CR .CR
@@ -333,9 +391,13 @@ @@ -338,9 +396,13 @@
/// # Safety /// # Safety
/// ///
/// - The user must ensure to provide a correct MMIO start address. /// - The user must ensure to provide a correct MMIO start address.
@ -1940,7 +1960,7 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
} }
} }
} }
@@ -355,6 +417,21 @@ @@ -360,6 +422,21 @@
Ok(()) Ok(())
} }
@ -1962,7 +1982,7 @@ diff -uNr 12_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
} }
impl console::interface::Write for PL011Uart { impl console::interface::Write for PL011Uart {
@@ -401,3 +478,24 @@ @@ -406,3 +483,24 @@
self.inner.lock(|inner| inner.chars_read) self.inner.lock(|inner| inner.chars_read)
} }
} }
@ -2376,15 +2396,17 @@ diff -uNr 12_integrated_testing/src/exception/asynchronous.rs 13_exceptions_part
diff -uNr 12_integrated_testing/src/lib.rs 13_exceptions_part2_peripheral_IRQs/src/lib.rs diff -uNr 12_integrated_testing/src/lib.rs 13_exceptions_part2_peripheral_IRQs/src/lib.rs
--- 12_integrated_testing/src/lib.rs --- 12_integrated_testing/src/lib.rs
+++ 13_exceptions_part2_peripheral_IRQs/src/lib.rs +++ 13_exceptions_part2_peripheral_IRQs/src/lib.rs
@@ -108,6 +108,7 @@ @@ -108,7 +108,9 @@
#![allow(clippy::upper_case_acronyms)] #![allow(clippy::upper_case_acronyms)]
#![allow(incomplete_features)] #![allow(incomplete_features)]
+#![feature(asm)] +#![feature(asm)]
#![feature(const_fn_fn_ptr_basics)] #![feature(const_fn_fn_ptr_basics)]
+#![feature(const_fn_trait_bound)]
#![feature(const_generics)] #![feature(const_generics)]
#![feature(const_panic)] #![feature(const_panic)]
@@ -134,6 +135,7 @@ #![feature(core_intrinsics)]
@@ -134,6 +136,7 @@
pub mod exception; pub mod exception;
pub mod memory; pub mod memory;
pub mod print; pub mod print;

@ -397,9 +397,9 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/exception.rs 14_
+ memory::Address, + memory::Address,
+}; +};
use core::{cell::UnsafeCell, fmt}; use core::{cell::UnsafeCell, fmt};
use cortex_a::{barrier, regs::*}; use cortex_a::{asm::barrier, registers::*};
use register::InMemoryRegister; use tock_registers::{
@@ -50,6 +54,20 @@ @@ -53,6 +57,20 @@
// Private Code // Private Code
//-------------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------------
@ -420,7 +420,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/exception.rs 14_
/// Prints verbose information about the exception and then panics. /// Prints verbose information about the exception and then panics.
fn default_exception_handler(e: &ExceptionContext) { fn default_exception_handler(e: &ExceptionContext) {
panic!( panic!(
@@ -166,7 +184,9 @@ @@ -169,7 +187,9 @@
writeln!(f, " - {}", ec_translation)?; writeln!(f, " - {}", ec_translation)?;
// Raw print of instruction specific syndrome. // Raw print of instruction specific syndrome.
@ -451,7 +451,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu/trans
}, },
}; };
use core::convert; use core::convert;
@@ -117,12 +120,9 @@ @@ -121,12 +124,9 @@
} }
trait StartAddr { trait StartAddr {
@ -465,7 +465,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu/trans
//-------------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------------
// Public Definitions // Public Definitions
//-------------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------------
@@ -137,10 +137,13 @@ @@ -141,10 +141,13 @@
/// Table descriptors, covering 512 MiB windows. /// Table descriptors, covering 512 MiB windows.
lvl2: [TableDescriptor; NUM_TABLES], lvl2: [TableDescriptor; NUM_TABLES],
@ -482,7 +482,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu/trans
//-------------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------------
// Private Code // Private Code
@@ -148,12 +151,8 @@ @@ -152,12 +155,8 @@
// The binary is still identity mapped, so we don't need to convert here. // The binary is still identity mapped, so we don't need to convert here.
impl<T, const N: usize> StartAddr for [T; N] { impl<T, const N: usize> StartAddr for [T; N] {
@ -497,7 +497,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu/trans
} }
} }
@@ -166,10 +165,10 @@ @@ -170,10 +169,10 @@
} }
/// Create an instance pointing to the supplied address. /// Create an instance pointing to the supplied address.
@ -510,7 +510,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu/trans
val.write( val.write(
STAGE1_TABLE_DESCRIPTOR::NEXT_LEVEL_TABLE_ADDR_64KiB.val(shifted as u64) STAGE1_TABLE_DESCRIPTOR::NEXT_LEVEL_TABLE_ADDR_64KiB.val(shifted as u64)
+ STAGE1_TABLE_DESCRIPTOR::TYPE::Table + STAGE1_TABLE_DESCRIPTOR::TYPE::Table
@@ -226,7 +225,10 @@ @@ -230,7 +229,10 @@
} }
/// Create an instance. /// Create an instance.
@ -522,7 +522,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu/trans
let val = InMemoryRegister::<u64, STAGE1_PAGE_DESCRIPTOR::Register>::new(0); let val = InMemoryRegister::<u64, STAGE1_PAGE_DESCRIPTOR::Register>::new(0);
let shifted = phys_output_addr as u64 >> Granule64KiB::SHIFT; let shifted = phys_output_addr as u64 >> Granule64KiB::SHIFT;
@@ -240,50 +242,193 @@ @@ -244,50 +246,193 @@
Self { value: val.get() } Self { value: val.get() }
} }
@ -687,7 +687,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu/trans
+ return Err("Virtual page is already mapped"); + return Err("Virtual page is already mapped");
} }
+ +
+ *page_descriptor = PageDescriptor::from_output_addr(phys_page.as_ptr(), &attr); + *page_descriptor = PageDescriptor::from_output_addr(phys_page.as_ptr(), attr);
} }
Ok(()) Ok(())
@ -733,7 +733,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu/trans
} }
} }
@@ -292,6 +437,9 @@ @@ -296,6 +441,9 @@
//-------------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------------
#[cfg(test)] #[cfg(test)]
@ -755,8 +755,8 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu.rs 14
+ memory::{mmu::TranslationGranule, Address, Physical}, + memory::{mmu::TranslationGranule, Address, Physical},
}; };
use core::intrinsics::unlikely; use core::intrinsics::unlikely;
use cortex_a::{barrier, regs::*}; use cortex_a::{asm::barrier, registers::*};
@@ -45,13 +45,6 @@ @@ -46,13 +46,6 @@
// Global instances // Global instances
//-------------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------------
@ -770,7 +770,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu.rs 14
static MMU: MemoryManagementUnit = MemoryManagementUnit; static MMU: MemoryManagementUnit = MemoryManagementUnit;
//-------------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------------
@@ -86,7 +79,7 @@ @@ -87,7 +80,7 @@
/// Configure various settings of stage 1 of the EL1 translation regime. /// Configure various settings of stage 1 of the EL1 translation regime.
fn configure_translation_control(&self) { fn configure_translation_control(&self) {
@ -779,7 +779,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu.rs 14
TCR_EL1.write( TCR_EL1.write(
TCR_EL1::TBI0::Used TCR_EL1::TBI0::Used
@@ -118,7 +111,10 @@ @@ -119,7 +112,10 @@
use memory::mmu::MMUEnableError; use memory::mmu::MMUEnableError;
impl memory::mmu::interface::MMU for MemoryManagementUnit { impl memory::mmu::interface::MMU for MemoryManagementUnit {
@ -791,7 +791,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu.rs 14
if unlikely(self.is_enabled()) { if unlikely(self.is_enabled()) {
return Err(MMUEnableError::AlreadyEnabled); return Err(MMUEnableError::AlreadyEnabled);
} }
@@ -133,13 +129,8 @@ @@ -134,13 +130,8 @@
// Prepare the memory attribute indirection register. // Prepare the memory attribute indirection register.
self.set_up_mair(); self.set_up_mair();
@ -806,7 +806,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/memory/mmu.rs 14
self.configure_translation_control(); self.configure_translation_control();
@@ -162,33 +153,3 @@ @@ -163,33 +154,3 @@
SCTLR_EL1.matches_all(SCTLR_EL1::M::Enable) SCTLR_EL1.matches_all(SCTLR_EL1::M::Enable)
} }
} }
@ -852,10 +852,10 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi
+use crate::{ +use crate::{
+ bsp::device_driver::common::MMIODerefWrapper, exception, synchronization::InitStateLock, + bsp::device_driver::common::MMIODerefWrapper, exception, synchronization::InitStateLock,
+}; +};
use register::{mmio::*, register_bitfields, register_structs}; use tock_registers::{
interfaces::{Readable, Writeable},
//-------------------------------------------------------------------------------------------------- register_bitfields, register_structs,
@@ -56,12 +58,13 @@ @@ -60,12 +62,13 @@
/// Representation of the GIC CPU interface. /// Representation of the GIC CPU interface.
pub struct GICC { pub struct GICC {
@ -870,7 +870,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi
impl GICC { impl GICC {
/// Create an instance. /// Create an instance.
@@ -71,10 +74,15 @@ @@ -75,10 +78,15 @@
/// - The user must ensure to provide a correct MMIO start address. /// - The user must ensure to provide a correct MMIO start address.
pub const unsafe fn new(mmio_start_addr: usize) -> Self { pub const unsafe fn new(mmio_start_addr: usize) -> Self {
Self { Self {
@ -887,7 +887,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi
/// Accept interrupts of any priority. /// Accept interrupts of any priority.
/// ///
/// Quoting the GICv2 Architecture Specification: /// Quoting the GICv2 Architecture Specification:
@@ -87,7 +95,9 @@ @@ -91,7 +99,9 @@
/// - GICC MMIO registers are banked per CPU core. It is therefore safe to have `&self` instead /// - GICC MMIO registers are banked per CPU core. It is therefore safe to have `&self` instead
/// of `&mut self`. /// of `&mut self`.
pub fn priority_accept_all(&self) { pub fn priority_accept_all(&self) {
@ -898,7 +898,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi
} }
/// Enable the interface - start accepting IRQs. /// Enable the interface - start accepting IRQs.
@@ -97,7 +107,9 @@ @@ -101,7 +111,9 @@
/// - GICC MMIO registers are banked per CPU core. It is therefore safe to have `&self` instead /// - GICC MMIO registers are banked per CPU core. It is therefore safe to have `&self` instead
/// of `&mut self`. /// of `&mut self`.
pub fn enable(&self) { pub fn enable(&self) {
@ -909,7 +909,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi
} }
/// Extract the number of the highest-priority pending IRQ. /// Extract the number of the highest-priority pending IRQ.
@@ -113,7 +125,8 @@ @@ -117,7 +129,8 @@
&self, &self,
_ic: &exception::asynchronous::IRQContext<'irq_context>, _ic: &exception::asynchronous::IRQContext<'irq_context>,
) -> usize { ) -> usize {
@ -919,7 +919,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi
} }
/// Complete handling of the currently active IRQ. /// Complete handling of the currently active IRQ.
@@ -132,6 +145,8 @@ @@ -136,6 +149,8 @@
irq_number: u32, irq_number: u32,
_ic: &exception::asynchronous::IRQContext<'irq_context>, _ic: &exception::asynchronous::IRQContext<'irq_context>,
) { ) {
@ -943,9 +943,9 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi
+ state, synchronization, + state, synchronization,
+ synchronization::{IRQSafeNullLock, InitStateLock}, + synchronization::{IRQSafeNullLock, InitStateLock},
}; };
use register::{mmio::*, register_bitfields, register_structs}; use tock_registers::{
interfaces::{Readable, Writeable},
@@ -79,7 +80,7 @@ @@ -83,7 +84,7 @@
shared_registers: IRQSafeNullLock<SharedRegisters>, shared_registers: IRQSafeNullLock<SharedRegisters>,
/// Access to banked registers is unguarded. /// Access to banked registers is unguarded.
@ -954,7 +954,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi
} }
//-------------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------------
@@ -116,6 +117,7 @@ @@ -120,6 +121,7 @@
//-------------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------------
// Public Code // Public Code
//-------------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------------
@ -962,7 +962,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi
use synchronization::interface::Mutex; use synchronization::interface::Mutex;
impl GICD { impl GICD {
@@ -127,10 +129,17 @@ @@ -131,10 +133,17 @@
pub const unsafe fn new(mmio_start_addr: usize) -> Self { pub const unsafe fn new(mmio_start_addr: usize) -> Self {
Self { Self {
shared_registers: IRQSafeNullLock::new(SharedRegisters::new(mmio_start_addr)), shared_registers: IRQSafeNullLock::new(SharedRegisters::new(mmio_start_addr)),
@ -981,7 +981,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi
/// Use a banked ITARGETSR to retrieve the executing core's GIC target mask. /// Use a banked ITARGETSR to retrieve the executing core's GIC target mask.
/// ///
/// Quoting the GICv2 Architecture Specification: /// Quoting the GICv2 Architecture Specification:
@@ -138,7 +147,8 @@ @@ -142,7 +151,8 @@
/// "GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that /// "GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that
/// corresponds only to the processor reading the register." /// corresponds only to the processor reading the register."
fn local_gic_target_mask(&self) -> u32 { fn local_gic_target_mask(&self) -> u32 {
@ -991,7 +991,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/arm/gicv2/gi
} }
/// Route all SPIs to the boot core and enable the distributor. /// Route all SPIs to the boot core and enable the distributor.
@@ -177,10 +187,10 @@ @@ -181,10 +191,10 @@
// Check if we are handling a private or shared IRQ. // Check if we are handling a private or shared IRQ.
match irq_num { match irq_num {
// Private. // Private.
@ -1096,10 +1096,10 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
synchronization::IRQSafeNullLock, synchronization::IRQSafeNullLock,
}; };
+use core::sync::atomic::{AtomicUsize, Ordering}; +use core::sync::atomic::{AtomicUsize, Ordering};
use register::{mmio::*, register_bitfields, register_structs}; use tock_registers::{
interfaces::{ReadWriteable, Writeable},
//-------------------------------------------------------------------------------------------------- register_bitfields, register_structs,
@@ -117,6 +118,8 @@ @@ -121,6 +122,8 @@
/// Representation of the GPIO HW. /// Representation of the GPIO HW.
pub struct GPIO { pub struct GPIO {
@ -1108,7 +1108,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
inner: IRQSafeNullLock<GPIOInner>, inner: IRQSafeNullLock<GPIOInner>,
} }
@@ -136,6 +139,19 @@ @@ -140,6 +143,19 @@
} }
} }
@ -1128,7 +1128,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
/// Disable pull-up/down on pins 14 and 15. /// Disable pull-up/down on pins 14 and 15.
#[cfg(feature = "bsp_rpi3")] #[cfg(feature = "bsp_rpi3")]
fn disable_pud_14_15_bcm2837(&mut self) { fn disable_pud_14_15_bcm2837(&mut self) {
@@ -190,10 +206,12 @@ @@ -194,10 +210,12 @@
/// ///
/// # Safety /// # Safety
/// ///
@ -1144,7 +1144,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
} }
} }
@@ -212,4 +230,26 @@ @@ -216,4 +234,26 @@
fn compatible(&self) -> &'static str { fn compatible(&self) -> &'static str {
"BCM GPIO" "BCM GPIO"
} }
@ -1175,13 +1175,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_interrupt_controller/peripheral_ic.rs 14_virtual_mem_part2_mmio_remap/src/bsp/device_driver/bcm/bcm2xxx_interrupt_controller/peripheral_ic.rs diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_interrupt_controller/peripheral_ic.rs 14_virtual_mem_part2_mmio_remap/src/bsp/device_driver/bcm/bcm2xxx_interrupt_controller/peripheral_ic.rs
--- 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_interrupt_controller/peripheral_ic.rs --- 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_interrupt_controller/peripheral_ic.rs
+++ 14_virtual_mem_part2_mmio_remap/src/bsp/device_driver/bcm/bcm2xxx_interrupt_controller/peripheral_ic.rs +++ 14_virtual_mem_part2_mmio_remap/src/bsp/device_driver/bcm/bcm2xxx_interrupt_controller/peripheral_ic.rs
@@ -2,12 +2,12 @@ @@ -7,7 +7,7 @@
//
// Copyright (c) 2020-2021 Andre Richter <andre.o.richter@gmail.com>
-//! Peripheral Interrupt regsler Driver.
+//! Peripheral Interrupt Controller Driver.
use super::{InterruptController, PendingIRQs, PeripheralIRQ}; use super::{InterruptController, PendingIRQs, PeripheralIRQ};
use crate::{ use crate::{
bsp::device_driver::common::MMIODerefWrapper, bsp::device_driver::common::MMIODerefWrapper,
@ -1189,8 +1183,8 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
+ driver, exception, memory, synchronization, + driver, exception, memory, synchronization,
synchronization::{IRQSafeNullLock, InitStateLock}, synchronization::{IRQSafeNullLock, InitStateLock},
}; };
use register::{mmio::*, register_structs}; use tock_registers::{
@@ -51,11 +51,13 @@ @@ -55,11 +55,13 @@
/// Representation of the peripheral interrupt controller. /// Representation of the peripheral interrupt controller.
pub struct PeripheralIC { pub struct PeripheralIC {
@ -1205,7 +1199,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
/// Stores registered IRQ handlers. Writable only during kernel init. RO afterwards. /// Stores registered IRQ handlers. Writable only during kernel init. RO afterwards.
handler_table: InitStateLock<HandlerTable>, handler_table: InitStateLock<HandlerTable>,
@@ -70,21 +72,26 @@ @@ -74,21 +76,26 @@
/// ///
/// # Safety /// # Safety
/// ///
@ -1239,7 +1233,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
} }
} }
@@ -93,6 +100,24 @@ @@ -97,6 +104,24 @@
//------------------------------------------------------------------------------ //------------------------------------------------------------------------------
use synchronization::interface::{Mutex, ReadWriteEx}; use synchronization::interface::{Mutex, ReadWriteEx};
@ -1322,10 +1316,10 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
+ fmt, + fmt,
+ sync::atomic::{AtomicUsize, Ordering}, + sync::atomic::{AtomicUsize, Ordering},
+}; +};
use register::{mmio::*, register_bitfields, register_structs}; use tock_registers::{
interfaces::{Readable, Writeable},
//-------------------------------------------------------------------------------------------------- register_bitfields, register_structs,
@@ -232,6 +235,8 @@ @@ -237,6 +240,8 @@
/// Representation of the UART. /// Representation of the UART.
pub struct PL011Uart { pub struct PL011Uart {
@ -1334,7 +1328,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
inner: IRQSafeNullLock<PL011UartInner>, inner: IRQSafeNullLock<PL011UartInner>,
irq_number: bsp::device_driver::IRQNumber, irq_number: bsp::device_driver::IRQNumber,
} }
@@ -271,7 +276,15 @@ @@ -276,7 +281,15 @@
/// genrated baud rate of `48_000_000 / (16 * 3.25) = 923_077`. /// genrated baud rate of `48_000_000 / (16 * 3.25) = 923_077`.
/// ///
/// Error = `((923_077 - 921_600) / 921_600) * 100 = 0.16modulo`. /// Error = `((923_077 - 921_600) / 921_600) * 100 = 0.16modulo`.
@ -1351,7 +1345,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
// Execution can arrive here while there are still characters queued in the TX FIFO and // Execution can arrive here while there are still characters queued in the TX FIFO and
// actively being sent out by the UART hardware. If the UART is turned off in this case, // actively being sent out by the UART hardware. If the UART is turned off in this case,
// those queued characters would be lost. // those queued characters would be lost.
@@ -313,6 +326,8 @@ @@ -318,6 +331,8 @@
self.registers self.registers
.CR .CR
.write(CR::UARTEN::Enabled + CR::TXE::Enabled + CR::RXE::Enabled); .write(CR::UARTEN::Enabled + CR::TXE::Enabled + CR::RXE::Enabled);
@ -1360,7 +1354,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
} }
/// Send a character. /// Send a character.
@@ -390,13 +405,18 @@ @@ -395,13 +410,18 @@
/// ///
/// # Safety /// # Safety
/// ///
@ -1382,7 +1376,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
irq_number, irq_number,
} }
} }
@@ -413,7 +433,13 @@ @@ -418,7 +438,13 @@
} }
unsafe fn init(&self) -> Result<(), &'static str> { unsafe fn init(&self) -> Result<(), &'static str> {
@ -1397,7 +1391,7 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
Ok(()) Ok(())
} }
@@ -432,6 +458,16 @@ @@ -437,6 +463,16 @@
Ok(()) Ok(())
} }
@ -2155,16 +2149,15 @@ diff -uNr 13_exceptions_part2_peripheral_IRQs/src/driver.rs 14_virtual_mem_part2
diff -uNr 13_exceptions_part2_peripheral_IRQs/src/lib.rs 14_virtual_mem_part2_mmio_remap/src/lib.rs diff -uNr 13_exceptions_part2_peripheral_IRQs/src/lib.rs 14_virtual_mem_part2_mmio_remap/src/lib.rs
--- 13_exceptions_part2_peripheral_IRQs/src/lib.rs --- 13_exceptions_part2_peripheral_IRQs/src/lib.rs
+++ 14_virtual_mem_part2_mmio_remap/src/lib.rs +++ 14_virtual_mem_part2_mmio_remap/src/lib.rs
@@ -109,6 +109,8 @@ @@ -109,6 +109,7 @@
#![allow(clippy::upper_case_acronyms)] #![allow(clippy::upper_case_acronyms)]
#![allow(incomplete_features)] #![allow(incomplete_features)]
#![feature(asm)] #![feature(asm)]
+#![feature(const_evaluatable_checked)] +#![feature(const_evaluatable_checked)]
+#![feature(const_fn)]
#![feature(const_fn_fn_ptr_basics)] #![feature(const_fn_fn_ptr_basics)]
#![feature(const_fn_trait_bound)]
#![feature(const_generics)] #![feature(const_generics)]
#![feature(const_panic)] @@ -130,6 +131,7 @@
@@ -129,6 +131,7 @@
mod synchronization; mod synchronization;
pub mod bsp; pub mod bsp;

@ -802,10 +802,10 @@ diff -uNr 14_virtual_mem_part2_mmio_remap/src/_arch/aarch64/cpu/boot.rs 15_virtu
+use crate::{cpu, memory, memory::Address}; +use crate::{cpu, memory, memory::Address};
+use core::intrinsics::unlikely; +use core::intrinsics::unlikely;
use cortex_a::{asm, regs::*}; use cortex_a::{asm, registers::*};
use tock_registers::interfaces::Writeable;
// Assembly counterpart to this file. @@ -70,9 +72,18 @@
@@ -69,9 +71,18 @@
/// ///
/// - Exception return from EL2 must must continue execution in EL1 with `kernel_init()`. /// - Exception return from EL2 must must continue execution in EL1 with `kernel_init()`.
#[no_mangle] #[no_mangle]
@ -857,10 +857,10 @@ diff -uNr 14_virtual_mem_part2_mmio_remap/src/_arch/aarch64/memory/mmu/translati
}; };
-use core::convert; -use core::convert;
+use core::convert::{self, TryInto}; +use core::convert::{self, TryInto};
use register::{register_bitfields, InMemoryRegister}; use tock_registers::{
interfaces::{Readable, Writeable},
//-------------------------------------------------------------------------------------------------- register_bitfields,
@@ -120,7 +120,7 @@ @@ -124,7 +124,7 @@
} }
trait StartAddr { trait StartAddr {
@ -869,7 +869,7 @@ diff -uNr 14_virtual_mem_part2_mmio_remap/src/_arch/aarch64/memory/mmu/translati
} }
//-------------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------------
@@ -149,9 +149,8 @@ @@ -153,9 +153,8 @@
// Private Code // Private Code
//-------------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------------
@ -880,7 +880,7 @@ diff -uNr 14_virtual_mem_part2_mmio_remap/src/_arch/aarch64/memory/mmu/translati
Address::new(self as *const _ as usize) Address::new(self as *const _ as usize)
} }
} }
@@ -269,7 +268,7 @@ @@ -273,7 +272,7 @@
/// Create an instance. /// Create an instance.
#[allow(clippy::assertions_on_constants)] #[allow(clippy::assertions_on_constants)]
@ -889,7 +889,7 @@ diff -uNr 14_virtual_mem_part2_mmio_remap/src/_arch/aarch64/memory/mmu/translati
assert!(bsp::memory::mmu::KernelGranule::SIZE == Granule64KiB::SIZE); assert!(bsp::memory::mmu::KernelGranule::SIZE == Granule64KiB::SIZE);
// Can't have a zero-sized address space. // Can't have a zero-sized address space.
@@ -278,11 +277,20 @@ @@ -282,11 +281,20 @@
Self { Self {
lvl3: [[PageDescriptor::new_zeroed(); 8192]; NUM_TABLES], lvl3: [[PageDescriptor::new_zeroed(); 8192]; NUM_TABLES],
lvl2: [TableDescriptor::new_zeroed(); NUM_TABLES], lvl2: [TableDescriptor::new_zeroed(); NUM_TABLES],
@ -912,7 +912,7 @@ diff -uNr 14_virtual_mem_part2_mmio_remap/src/_arch/aarch64/memory/mmu/translati
/// The start address of the table's MMIO range. /// The start address of the table's MMIO range.
#[inline(always)] #[inline(always)]
fn mmio_start_addr(&self) -> Address<Virtual> { fn mmio_start_addr(&self) -> Address<Virtual> {
@@ -338,24 +346,26 @@ @@ -342,24 +350,26 @@
impl<const NUM_TABLES: usize> memory::mmu::translation_table::interface::TranslationTable impl<const NUM_TABLES: usize> memory::mmu::translation_table::interface::TranslationTable
for FixedSizeTranslationTable<NUM_TABLES> for FixedSizeTranslationTable<NUM_TABLES>
{ {
@ -958,8 +958,8 @@ diff -uNr 14_virtual_mem_part2_mmio_remap/src/_arch/aarch64/memory/mmu.rs 15_vir
+ memory::{mmu::TranslationGranule, Address, Physical, Virtual}, + memory::{mmu::TranslationGranule, Address, Physical, Virtual},
}; };
use core::intrinsics::unlikely; use core::intrinsics::unlikely;
use cortex_a::{barrier, regs::*}; use cortex_a::{asm::barrier, registers::*};
@@ -108,7 +108,7 @@ @@ -109,7 +109,7 @@
//------------------------------------------------------------------------------ //------------------------------------------------------------------------------
// OS Interface Code // OS Interface Code
//------------------------------------------------------------------------------ //------------------------------------------------------------------------------
@ -968,7 +968,7 @@ diff -uNr 14_virtual_mem_part2_mmio_remap/src/_arch/aarch64/memory/mmu.rs 15_vir
impl memory::mmu::interface::MMU for MemoryManagementUnit { impl memory::mmu::interface::MMU for MemoryManagementUnit {
unsafe fn enable_mmu_and_caching( unsafe fn enable_mmu_and_caching(
@@ -152,4 +152,31 @@ @@ -153,4 +153,31 @@
fn is_enabled(&self) -> bool { fn is_enabled(&self) -> bool {
SCTLR_EL1.matches_all(SCTLR_EL1::M::Enable) SCTLR_EL1.matches_all(SCTLR_EL1::M::Enable)
} }

@ -246,7 +246,7 @@ diff -uNr 15_virtual_mem_part3_precomputed_tables/Cargo.toml 16_virtual_mem_part
diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/cpu/boot.rs 16_virtual_mem_part4_higher_half_kernel/src/_arch/aarch64/cpu/boot.rs diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/cpu/boot.rs 16_virtual_mem_part4_higher_half_kernel/src/_arch/aarch64/cpu/boot.rs
--- 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/cpu/boot.rs --- 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/cpu/boot.rs
+++ 16_virtual_mem_part4_higher_half_kernel/src/_arch/aarch64/cpu/boot.rs +++ 16_virtual_mem_part4_higher_half_kernel/src/_arch/aarch64/cpu/boot.rs
@@ -29,7 +29,10 @@ @@ -30,7 +30,10 @@
/// - The `bss` section is not initialized yet. The code must not use or reference it in any way. /// - The `bss` section is not initialized yet. The code must not use or reference it in any way.
/// - The HW state of EL1 must be prepared in a sound way. /// - The HW state of EL1 must be prepared in a sound way.
#[inline(always)] #[inline(always)]
@ -258,7 +258,7 @@ diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/cpu/boot.rs
// Enable timer counter registers for EL1. // Enable timer counter registers for EL1.
CNTHCTL_EL2.write(CNTHCTL_EL2::EL1PCEN::SET + CNTHCTL_EL2::EL1PCTEN::SET); CNTHCTL_EL2.write(CNTHCTL_EL2::EL1PCEN::SET + CNTHCTL_EL2::EL1PCTEN::SET);
@@ -52,11 +55,11 @@ @@ -53,11 +56,11 @@
); );
// Second, let the link register point to kernel_init(). // Second, let the link register point to kernel_init().
@ -272,7 +272,7 @@ diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/cpu/boot.rs
} }
//-------------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------------
@@ -73,9 +76,13 @@ @@ -74,9 +77,13 @@
#[no_mangle] #[no_mangle]
pub unsafe extern "C" fn _start_rust( pub unsafe extern "C" fn _start_rust(
phys_kernel_tables_base_addr: u64, phys_kernel_tables_base_addr: u64,
@ -288,7 +288,7 @@ diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/cpu/boot.rs
// Turn on the MMU for EL1. // Turn on the MMU for EL1.
let addr = Address::new(phys_kernel_tables_base_addr as usize); let addr = Address::new(phys_kernel_tables_base_addr as usize);
@@ -83,6 +90,7 @@ @@ -84,6 +91,7 @@
cpu::wait_forever(); cpu::wait_forever();
} }
@ -352,7 +352,7 @@ diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/cpu/boot.s 1
diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/memory/mmu/translation_table.rs 16_virtual_mem_part4_higher_half_kernel/src/_arch/aarch64/memory/mmu/translation_table.rs diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/memory/mmu/translation_table.rs 16_virtual_mem_part4_higher_half_kernel/src/_arch/aarch64/memory/mmu/translation_table.rs
--- 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/memory/mmu/translation_table.rs --- 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/memory/mmu/translation_table.rs
+++ 16_virtual_mem_part4_higher_half_kernel/src/_arch/aarch64/memory/mmu/translation_table.rs +++ 16_virtual_mem_part4_higher_half_kernel/src/_arch/aarch64/memory/mmu/translation_table.rs
@@ -131,7 +131,7 @@ @@ -135,7 +135,7 @@
/// aligned, so the lvl3 is put first. /// aligned, so the lvl3 is put first.
#[repr(C)] #[repr(C)]
#[repr(align(65536))] #[repr(align(65536))]
@ -361,7 +361,7 @@ diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/memory/mmu/t
/// Page descriptors, covering 64 KiB windows per entry. /// Page descriptors, covering 64 KiB windows per entry.
lvl3: [[PageDescriptor; 8192]; NUM_TABLES], lvl3: [[PageDescriptor; 8192]; NUM_TABLES],
@@ -258,14 +258,23 @@ @@ -262,14 +262,23 @@
where where
[u8; Self::SIZE >> Granule512MiB::SHIFT]: Sized, [u8; Self::SIZE >> Granule512MiB::SHIFT]: Sized,
{ {
@ -387,7 +387,7 @@ diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/memory/mmu/t
/// Create an instance. /// Create an instance.
#[allow(clippy::assertions_on_constants)] #[allow(clippy::assertions_on_constants)]
const fn _new(for_precompute: bool) -> Self { const fn _new(for_precompute: bool) -> Self {
@@ -294,20 +303,32 @@ @@ -298,20 +307,32 @@
/// The start address of the table's MMIO range. /// The start address of the table's MMIO range.
#[inline(always)] #[inline(always)]
fn mmio_start_addr(&self) -> Address<Virtual> { fn mmio_start_addr(&self) -> Address<Virtual> {
@ -424,7 +424,7 @@ diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/memory/mmu/t
} }
/// Helper to calculate the lvl2 and lvl3 indices from an address. /// Helper to calculate the lvl2 and lvl3 indices from an address.
@@ -316,7 +337,12 @@ @@ -320,7 +341,12 @@
&self, &self,
addr: *const Page<Virtual>, addr: *const Page<Virtual>,
) -> Result<(usize, usize), &'static str> { ) -> Result<(usize, usize), &'static str> {
@ -438,7 +438,7 @@ diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/memory/mmu/t
let lvl2_index = addr >> Granule512MiB::SHIFT; let lvl2_index = addr >> Granule512MiB::SHIFT;
let lvl3_index = (addr & Granule512MiB::MASK) >> Granule64KiB::SHIFT; let lvl3_index = (addr & Granule512MiB::MASK) >> Granule64KiB::SHIFT;
@@ -343,8 +369,9 @@ @@ -347,8 +373,9 @@
// OS Interface Code // OS Interface Code
//------------------------------------------------------------------------------ //------------------------------------------------------------------------------
@ -450,7 +450,7 @@ diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/memory/mmu/t
{ {
fn init(&mut self) -> Result<(), &'static str> { fn init(&mut self) -> Result<(), &'static str> {
if self.initialized { if self.initialized {
@@ -419,12 +446,16 @@ @@ -423,12 +450,16 @@
return Err("Not enough MMIO space left"); return Err("Not enough MMIO space left");
} }
@ -468,7 +468,7 @@ diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/memory/mmu/t
Ok(PageSliceDescriptor::from_addr(addr, num_pages)) Ok(PageSliceDescriptor::from_addr(addr, num_pages))
} }
@@ -447,7 +478,7 @@ @@ -451,7 +482,7 @@
//-------------------------------------------------------------------------------------------------- //--------------------------------------------------------------------------------------------------
#[cfg(test)] #[cfg(test)]
@ -481,7 +481,7 @@ diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/memory/mmu/t
diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/memory/mmu.rs 16_virtual_mem_part4_higher_half_kernel/src/_arch/aarch64/memory/mmu.rs diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/memory/mmu.rs 16_virtual_mem_part4_higher_half_kernel/src/_arch/aarch64/memory/mmu.rs
--- 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/memory/mmu.rs --- 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/memory/mmu.rs
+++ 16_virtual_mem_part4_higher_half_kernel/src/_arch/aarch64/memory/mmu.rs +++ 16_virtual_mem_part4_higher_half_kernel/src/_arch/aarch64/memory/mmu.rs
@@ -65,6 +65,7 @@ @@ -66,6 +66,7 @@
impl MemoryManagementUnit { impl MemoryManagementUnit {
/// Setup function for the MAIR_EL1 register. /// Setup function for the MAIR_EL1 register.
@ -489,7 +489,7 @@ diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/memory/mmu.r
fn set_up_mair(&self) { fn set_up_mair(&self) {
// Define the memory types being mapped. // Define the memory types being mapped.
MAIR_EL1.write( MAIR_EL1.write(
@@ -78,20 +79,21 @@ @@ -79,20 +80,21 @@
} }
/// Configure various settings of stage 1 of the EL1 translation regime. /// Configure various settings of stage 1 of the EL1 translation regime.
@ -521,7 +521,7 @@ diff -uNr 15_virtual_mem_part3_precomputed_tables/src/_arch/aarch64/memory/mmu.r
); );
} }
} }
@@ -130,7 +132,7 @@ @@ -131,7 +133,7 @@
self.set_up_mair(); self.set_up_mair();
// Set the "Translation Table Base Register". // Set the "Translation Table Base Register".

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