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@ -32,17 +32,17 @@ const UART_BASE: u32 = MMIO_BASE + 0x20_1000;
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// PL011 UART registers
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#[allow(non_snake_case)]
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#[repr(C, packed)]
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#[repr(C)]
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struct Registers {
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DR: RW<u32>, // 0x00
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reserved0: [u8; 0x14], // 0x04
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__reserved_0: [u32; 5], // 0x04
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FR: RO<u32>, // 0x18
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reserved1: u64, // 0x1C
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__reserved_1: [u32; 2], // 0x1c
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IBRD: WO<u32>, // 0x24
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FBRD: WO<u32>, // 0x28
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LCRH: WO<u32>, // 0x2C
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CR: WO<u32>, // 0x30
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reserved3: [u8; 0x10], // 0x34
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__reserved_2: [u32; 4], // 0x34
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ICR: WO<u32>, // 0x44
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}
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