Cleanup register definitions

pull/4/head
Andre Richter 6 years ago
parent d2a16a6c71
commit a772630b3b

@ -30,11 +30,11 @@ const MINI_UART_BASE: u32 = MMIO_BASE + 0x21_5000;
/// Auxilary mini UART registers
#[allow(non_snake_case)]
#[repr(C, packed)]
#[repr(C)]
struct Registers {
_reserved0: u32, // 0x00
__reserved_0: u32, // 0x00
ENABLES: RW<u32>, // 0x04
_reserved1: [u8; 0x38], // 0x08
__reserved_1: [u32; 14], // 0x08
MU_IO: RW<u32>, // 0x40
MU_IER: RW<u32>, // 0x44
MU_IIR: RW<u32>, // 0x48

@ -28,10 +28,10 @@ use volatile_register::{RO, WO};
pub const VIDEOCORE_MBOX: u32 = MMIO_BASE + 0xB880;
#[allow(non_snake_case)]
#[repr(C, packed)]
#[repr(C)]
pub struct Registers {
READ: RO<u32>, // 0x00
reserved: [u8; 0xC], // 0x04
__reserved_0: [u32; 3], // 0x04
POLL: RO<u32>, // 0x10
SENDER: RO<u32>, // 0x14
STATUS: RO<u32>, // 0x18

@ -30,11 +30,11 @@ const MINI_UART_BASE: u32 = MMIO_BASE + 0x21_5000;
/// Auxilary mini UART registers
#[allow(non_snake_case)]
#[repr(C, packed)]
#[repr(C)]
struct Registers {
_reserved0: u32, // 0x00
__reserved_0: u32, // 0x00
ENABLES: RW<u32>, // 0x04
_reserved1: [u8; 0x38], // 0x08
__reserved_1: [u32; 14], // 0x08
MU_IO: RW<u32>, // 0x40
MU_IER: RW<u32>, // 0x44
MU_IIR: RW<u32>, // 0x48

@ -28,10 +28,10 @@ use volatile_register::{RO, WO};
pub const VIDEOCORE_MBOX: u32 = MMIO_BASE + 0xB880;
#[allow(non_snake_case)]
#[repr(C, packed)]
#[repr(C)]
pub struct Registers {
READ: RO<u32>, // 0x00
reserved: [u8; 0xC], // 0x04
__reserved_0: [u32; 3], // 0x04
POLL: RO<u32>, // 0x10
SENDER: RO<u32>, // 0x14
STATUS: RO<u32>, // 0x18

@ -32,17 +32,17 @@ const UART_BASE: u32 = MMIO_BASE + 0x20_1000;
// PL011 UART registers
#[allow(non_snake_case)]
#[repr(C, packed)]
#[repr(C)]
struct Registers {
DR: RW<u32>, // 0x00
reserved0: [u8; 0x14], // 0x04
__reserved_0: [u32; 5], // 0x04
FR: RO<u32>, // 0x18
reserved1: u64, // 0x1C
__reserved_1: [u32; 2], // 0x1c
IBRD: WO<u32>, // 0x24
FBRD: WO<u32>, // 0x28
LCRH: WO<u32>, // 0x2C
CR: WO<u32>, // 0x30
reserved3: [u8; 0x10], // 0x34
__reserved_2: [u32; 4], // 0x34
ICR: WO<u32>, // 0x44
}

@ -28,10 +28,10 @@ use volatile_register::{RO, WO};
pub const VIDEOCORE_MBOX: u32 = MMIO_BASE + 0xB880;
#[allow(non_snake_case)]
#[repr(C, packed)]
#[repr(C)]
pub struct Registers {
READ: RO<u32>, // 0x00
reserved: [u8; 0xC], // 0x04
__reserved_0: [u32; 3], // 0x04
POLL: RO<u32>, // 0x10
SENDER: RO<u32>, // 0x14
STATUS: RO<u32>, // 0x18

@ -33,7 +33,7 @@ struct Registers {
CTRL: RW<u32>, // 0x00
STATUS: RW<u32>, // 0x04
DATA: RO<u32>, // 0x08
_reserved: u32, // 0x0c
__reserved_0: u32, // 0x0c
INT_MASK: RW<u32>, // 0x10
}

@ -32,17 +32,17 @@ const UART_BASE: u32 = MMIO_BASE + 0x20_1000;
// PL011 UART registers
#[allow(non_snake_case)]
#[repr(C, packed)]
#[repr(C)]
struct Registers {
DR: RW<u32>, // 0x00
reserved0: [u8; 0x14], // 0x04
__reserved_0: [u32; 5], // 0x04
FR: RO<u32>, // 0x18
reserved1: u64, // 0x1C
__reserved_1: [u32; 2], // 0x1c
IBRD: WO<u32>, // 0x24
FBRD: WO<u32>, // 0x28
LCRH: WO<u32>, // 0x2C
CR: WO<u32>, // 0x30
reserved3: [u8; 0x10], // 0x34
__reserved_2: [u32; 4], // 0x34
ICR: WO<u32>, // 0x44
}

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