Archives
/
rust-raspberrypi-OS-tutorials
mirror of https://github.com/rust-embedded/rust-raspberrypi-OS-tutorials
2
0
Fork 0
Code Issues Projects Releases Wiki Activity

Cleanup register definitions

Browse Source
pull/4/head
Andre Richter 6 years ago
parent d2a16a6c71
commit a772630b3b
8 changed files with 77 additions and 77 deletions
Show Stats Download Patch File Download Diff File

30
03_uart1/src/uart.rs
Unescape Escape View File

@ -30,22 +30,22 @@ const MINI_UART_BASE: u32 = MMIO_BASE + 0x21_5000;
/// Auxilary mini UART registers /// Auxilary mini UART registers
#[allow(non_snake_case)] #[allow(non_snake_case)]
#[repr(C, packed)] #[repr(C)]
struct Registers { struct Registers {
_reserved0: u32, // 0x00 __reserved_0: u32, // 0x00
ENABLES: RW<u32>, // 0x04 ENABLES: RW<u32>, // 0x04
_reserved1: [u8; 0x38], // 0x08 __reserved_1: [u32; 14], // 0x08
MU_IO: RW<u32>, // 0x40 MU_IO: RW<u32>, // 0x40
MU_IER: RW<u32>, // 0x44 MU_IER: RW<u32>, // 0x44
MU_IIR: RW<u32>, // 0x48 MU_IIR: RW<u32>, // 0x48
MU_LCR: RW<u32>, // 0x4C MU_LCR: RW<u32>, // 0x4C
MU_MCR: RW<u32>, // 0x50 MU_MCR: RW<u32>, // 0x50
MU_LSR: RW<u32>, // 0x54 MU_LSR: RW<u32>, // 0x54
MU_MSR: RW<u32>, // 0x58 MU_MSR: RW<u32>, // 0x58
MU_SCRATCH: RW<u32>, // 0x5C MU_SCRATCH: RW<u32>, // 0x5C
MU_CNTL: RW<u32>, // 0x60 MU_CNTL: RW<u32>, // 0x60
MU_STAT: RW<u32>, // 0x64 MU_STAT: RW<u32>, // 0x64
MU_BAUD: RW<u32>, // 0x68 MU_BAUD: RW<u32>, // 0x68
} }
pub struct MiniUart { pub struct MiniUart {

16
04_mailboxes/src/mbox.rs
Unescape Escape View File

@ -28,15 +28,15 @@ use volatile_register::{RO, WO};
pub const VIDEOCORE_MBOX: u32 = MMIO_BASE + 0xB880; pub const VIDEOCORE_MBOX: u32 = MMIO_BASE + 0xB880;
#[allow(non_snake_case)] #[allow(non_snake_case)]
#[repr(C, packed)] #[repr(C)]
pub struct Registers { pub struct Registers {
READ: RO<u32>, // 0x00 READ: RO<u32>, // 0x00
reserved: [u8; 0xC], // 0x04 __reserved_0: [u32; 3], // 0x04
POLL: RO<u32>, // 0x10 POLL: RO<u32>, // 0x10
SENDER: RO<u32>, // 0x14 SENDER: RO<u32>, // 0x14
STATUS: RO<u32>, // 0x18 STATUS: RO<u32>, // 0x18
CONFIG: RO<u32>, // 0x1C CONFIG: RO<u32>, // 0x1C
WRITE: WO<u32>, // 0x20 WRITE: WO<u32>, // 0x20
} }
// Custom errors // Custom errors

30
04_mailboxes/src/uart.rs
Unescape Escape View File

@ -30,22 +30,22 @@ const MINI_UART_BASE: u32 = MMIO_BASE + 0x21_5000;
/// Auxilary mini UART registers /// Auxilary mini UART registers
#[allow(non_snake_case)] #[allow(non_snake_case)]
#[repr(C, packed)] #[repr(C)]
struct Registers { struct Registers {
_reserved0: u32, // 0x00 __reserved_0: u32, // 0x00
ENABLES: RW<u32>, // 0x04 ENABLES: RW<u32>, // 0x04
_reserved1: [u8; 0x38], // 0x08 __reserved_1: [u32; 14], // 0x08
MU_IO: RW<u32>, // 0x40 MU_IO: RW<u32>, // 0x40
MU_IER: RW<u32>, // 0x44 MU_IER: RW<u32>, // 0x44
MU_IIR: RW<u32>, // 0x48 MU_IIR: RW<u32>, // 0x48
MU_LCR: RW<u32>, // 0x4C MU_LCR: RW<u32>, // 0x4C
MU_MCR: RW<u32>, // 0x50 MU_MCR: RW<u32>, // 0x50
MU_LSR: RW<u32>, // 0x54 MU_LSR: RW<u32>, // 0x54
MU_MSR: RW<u32>, // 0x58 MU_MSR: RW<u32>, // 0x58
MU_SCRATCH: RW<u32>, // 0x5C MU_SCRATCH: RW<u32>, // 0x5C
MU_CNTL: RW<u32>, // 0x60 MU_CNTL: RW<u32>, // 0x60
MU_STAT: RW<u32>, // 0x64 MU_STAT: RW<u32>, // 0x64
MU_BAUD: RW<u32>, // 0x68 MU_BAUD: RW<u32>, // 0x68
} }
pub struct MiniUart { pub struct MiniUart {

16
05_uart0/src/mbox.rs
Unescape Escape View File

@ -28,15 +28,15 @@ use volatile_register::{RO, WO};
pub const VIDEOCORE_MBOX: u32 = MMIO_BASE + 0xB880; pub const VIDEOCORE_MBOX: u32 = MMIO_BASE + 0xB880;
#[allow(non_snake_case)] #[allow(non_snake_case)]
#[repr(C, packed)] #[repr(C)]
pub struct Registers { pub struct Registers {
READ: RO<u32>, // 0x00 READ: RO<u32>, // 0x00
reserved: [u8; 0xC], // 0x04 __reserved_0: [u32; 3], // 0x04
POLL: RO<u32>, // 0x10 POLL: RO<u32>, // 0x10
SENDER: RO<u32>, // 0x14 SENDER: RO<u32>, // 0x14
STATUS: RO<u32>, // 0x18 STATUS: RO<u32>, // 0x18
CONFIG: RO<u32>, // 0x1C CONFIG: RO<u32>, // 0x1C
WRITE: WO<u32>, // 0x20 WRITE: WO<u32>, // 0x20
} }
// Custom errors // Custom errors

22
05_uart0/src/uart.rs
Unescape Escape View File

@ -32,18 +32,18 @@ const UART_BASE: u32 = MMIO_BASE + 0x20_1000;
// PL011 UART registers // PL011 UART registers
#[allow(non_snake_case)] #[allow(non_snake_case)]
#[repr(C, packed)] #[repr(C)]
struct Registers { struct Registers {
DR: RW<u32>, // 0x00 DR: RW<u32>, // 0x00
reserved0: [u8; 0x14], // 0x04 __reserved_0: [u32; 5], // 0x04
FR: RO<u32>, // 0x18 FR: RO<u32>, // 0x18
reserved1: u64, // 0x1C __reserved_1: [u32; 2], // 0x1c
IBRD: WO<u32>, // 0x24 IBRD: WO<u32>, // 0x24
FBRD: WO<u32>, // 0x28 FBRD: WO<u32>, // 0x28
LCRH: WO<u32>, // 0x2C LCRH: WO<u32>, // 0x2C
CR: WO<u32>, // 0x30 CR: WO<u32>, // 0x30
reserved3: [u8; 0x10], // 0x34 __reserved_2: [u32; 4], // 0x34
ICR: WO<u32>, // 0x44 ICR: WO<u32>, // 0x44
} }
pub enum UartError { pub enum UartError {

16
06_random/src/mbox.rs
Unescape Escape View File

@ -28,15 +28,15 @@ use volatile_register::{RO, WO};
pub const VIDEOCORE_MBOX: u32 = MMIO_BASE + 0xB880; pub const VIDEOCORE_MBOX: u32 = MMIO_BASE + 0xB880;
#[allow(non_snake_case)] #[allow(non_snake_case)]
#[repr(C, packed)] #[repr(C)]
pub struct Registers { pub struct Registers {
READ: RO<u32>, // 0x00 READ: RO<u32>, // 0x00
reserved: [u8; 0xC], // 0x04 __reserved_0: [u32; 3], // 0x04
POLL: RO<u32>, // 0x10 POLL: RO<u32>, // 0x10
SENDER: RO<u32>, // 0x14 SENDER: RO<u32>, // 0x14
STATUS: RO<u32>, // 0x18 STATUS: RO<u32>, // 0x18
CONFIG: RO<u32>, // 0x1C CONFIG: RO<u32>, // 0x1C
WRITE: WO<u32>, // 0x20 WRITE: WO<u32>, // 0x20
} }
// Custom errors // Custom errors

2
06_random/src/rand.rs
Unescape Escape View File

@ -33,7 +33,7 @@ struct Registers {
CTRL: RW<u32>, // 0x00 CTRL: RW<u32>, // 0x00
STATUS: RW<u32>, // 0x04 STATUS: RW<u32>, // 0x04
DATA: RO<u32>, // 0x08 DATA: RO<u32>, // 0x08
_reserved: u32, // 0x0c __reserved_0: u32, // 0x0c
INT_MASK: RW<u32>, // 0x10 INT_MASK: RW<u32>, // 0x10
} }

22
06_random/src/uart.rs
Unescape Escape View File

@ -32,18 +32,18 @@ const UART_BASE: u32 = MMIO_BASE + 0x20_1000;
// PL011 UART registers // PL011 UART registers
#[allow(non_snake_case)] #[allow(non_snake_case)]
#[repr(C, packed)] #[repr(C)]
struct Registers { struct Registers {
DR: RW<u32>, // 0x00 DR: RW<u32>, // 0x00
reserved0: [u8; 0x14], // 0x04 __reserved_0: [u32; 5], // 0x04
FR: RO<u32>, // 0x18 FR: RO<u32>, // 0x18
reserved1: u64, // 0x1C __reserved_1: [u32; 2], // 0x1c
IBRD: WO<u32>, // 0x24 IBRD: WO<u32>, // 0x24
FBRD: WO<u32>, // 0x28 FBRD: WO<u32>, // 0x28
LCRH: WO<u32>, // 0x2C LCRH: WO<u32>, // 0x2C
CR: WO<u32>, // 0x30 CR: WO<u32>, // 0x30
reserved3: [u8; 0x10], // 0x34 __reserved_2: [u32; 4], // 0x34
ICR: WO<u32>, // 0x44 ICR: WO<u32>, // 0x44
} }
pub enum UartError { pub enum UartError {

Write Preview
Loading…
Cancel
Save