Minor corrections

0A_power/Cargo.lock

@@ -1,3 +1,5 @@
+# This file is automatically @generated by Cargo.
+# It is not intended for manual editing.
 [[package]]
 name = "cortex-a"
 version = "2.3.1"

0A_power/src/power.rs

@@ -1,7 +1,7 @@
 /*
  * MIT License
  *
- * Copyright (c) 2018 Andre Richter <andre.o.richter@gmail.com>
+ * Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -95,7 +95,7 @@ impl Power {
             compiler_fence(Ordering::Release);
 
             if mbox.call(mbox::channel::PROP).is_err() {
-                return Err(PowerError::MailboxError); // Abort if UART clocks couldn't be set
+                return Err(PowerError::MailboxError);
             };
         }
 

0B_hw_debug_JTAG/README.md

@@ -6,7 +6,7 @@ processor's `Exception Level` or introducing `virtual memory`.
 
 A hardware based debugger can sometimes be the last resort when searching for a
 tricky bug. Especially for debugging intricate, architecture-specific HW issues,
-it will be handy, because in this area `QEMU` sometimes can not help, because it
+it will be handy, because in this area `QEMU` sometimes can not help, since it
 abstracts certain features of our RPi's HW and doesn't simulate down to the very
 last bit.
 
@@ -15,6 +15,11 @@ through our kernel on the real HW. How cool is that?!
 
 ![JTAG live demo](../doc/jtag_demo.gif)
 
+## Outline
+
+Functionally, this tutorial is the same as the previous one, where we reset or
+power down the RPi. Around that, we add infrastructure for JTAG debugging.
+
 ## Hardware
 
 Unlike microcontroller boards like the `STM32F3DISCOVERY`, which is used in our
@@ -185,7 +190,7 @@ the minimal JTAG pin enablement binary).
 >>> break _boot_cores
 Breakpoint 1 at 0x80000
 >>> target remote :3333   # Connect to OpenOCD, raspi3.core0
->>> load kernel8_for_jtag # Load the kernel into the Raspi's DRAM over JTAG.
+>>> load                  # Load the kernel into the Raspi's DRAM over JTAG.
 Loading section .text, size 0x6cc lma 0x80000
 Loading section .rodata, size 0x9a lma 0x806cc
 Start address 0x80000, load size 1894

0B_hw_debug_JTAG/src/power.rs

@@ -95,7 +95,7 @@ impl Power {
             compiler_fence(Ordering::Release);
 
             if mbox.call(mbox::channel::PROP).is_err() {
-                return Err(PowerError::MailboxError); // Abort if UART clocks couldn't be set
+                return Err(PowerError::MailboxError);
             };
         }
 

docker/raspi3-openocd/rpi3.cfg

@@ -1,5 +1,6 @@
 # Script from
 # https://www.suse.com/c/debugging-raspberry-pi-3-with-jtag/
+# with minor adaptions.
 
 transport select jtag