From 0844823805c52849a298c71bdc4376a8c08edc7c Mon Sep 17 00:00:00 2001 From: Andre Richter Date: Sun, 10 Mar 2019 13:40:28 +0100 Subject: [PATCH] Minor corrections --- 0A_power/Cargo.lock | 2 ++ 0A_power/src/power.rs | 4 ++-- 0B_hw_debug_JTAG/README.md | 9 +++++++-- 0B_hw_debug_JTAG/src/power.rs | 2 +- docker/raspi3-openocd/rpi3.cfg | 1 + 5 files changed, 13 insertions(+), 5 deletions(-) diff --git a/0A_power/Cargo.lock b/0A_power/Cargo.lock index 16ef5e23..8d47f89a 100644 --- a/0A_power/Cargo.lock +++ b/0A_power/Cargo.lock @@ -1,3 +1,5 @@ +# This file is automatically @generated by Cargo. +# It is not intended for manual editing. [[package]] name = "cortex-a" version = "2.3.1" diff --git a/0A_power/src/power.rs b/0A_power/src/power.rs index 4cce72d1..4b555a05 100644 --- a/0A_power/src/power.rs +++ b/0A_power/src/power.rs @@ -1,7 +1,7 @@ /* * MIT License * - * Copyright (c) 2018 Andre Richter + * Copyright (c) 2018-2019 Andre Richter * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -95,7 +95,7 @@ impl Power { compiler_fence(Ordering::Release); if mbox.call(mbox::channel::PROP).is_err() { - return Err(PowerError::MailboxError); // Abort if UART clocks couldn't be set + return Err(PowerError::MailboxError); }; } diff --git a/0B_hw_debug_JTAG/README.md b/0B_hw_debug_JTAG/README.md index 74ae9a45..5812d673 100644 --- a/0B_hw_debug_JTAG/README.md +++ b/0B_hw_debug_JTAG/README.md @@ -6,7 +6,7 @@ processor's `Exception Level` or introducing `virtual memory`. A hardware based debugger can sometimes be the last resort when searching for a tricky bug. Especially for debugging intricate, architecture-specific HW issues, -it will be handy, because in this area `QEMU` sometimes can not help, because it +it will be handy, because in this area `QEMU` sometimes can not help, since it abstracts certain features of our RPi's HW and doesn't simulate down to the very last bit. @@ -15,6 +15,11 @@ through our kernel on the real HW. How cool is that?! ![JTAG live demo](../doc/jtag_demo.gif) +## Outline + +Functionally, this tutorial is the same as the previous one, where we reset or +power down the RPi. Around that, we add infrastructure for JTAG debugging. + ## Hardware Unlike microcontroller boards like the `STM32F3DISCOVERY`, which is used in our @@ -185,7 +190,7 @@ the minimal JTAG pin enablement binary). >>> break _boot_cores Breakpoint 1 at 0x80000 >>> target remote :3333 # Connect to OpenOCD, raspi3.core0 ->>> load kernel8_for_jtag # Load the kernel into the Raspi's DRAM over JTAG. +>>> load # Load the kernel into the Raspi's DRAM over JTAG. Loading section .text, size 0x6cc lma 0x80000 Loading section .rodata, size 0x9a lma 0x806cc Start address 0x80000, load size 1894 diff --git a/0B_hw_debug_JTAG/src/power.rs b/0B_hw_debug_JTAG/src/power.rs index 9a61a762..4b555a05 100644 --- a/0B_hw_debug_JTAG/src/power.rs +++ b/0B_hw_debug_JTAG/src/power.rs @@ -95,7 +95,7 @@ impl Power { compiler_fence(Ordering::Release); if mbox.call(mbox::channel::PROP).is_err() { - return Err(PowerError::MailboxError); // Abort if UART clocks couldn't be set + return Err(PowerError::MailboxError); }; } diff --git a/docker/raspi3-openocd/rpi3.cfg b/docker/raspi3-openocd/rpi3.cfg index e8976e92..c0a2e982 100644 --- a/docker/raspi3-openocd/rpi3.cfg +++ b/docker/raspi3-openocd/rpi3.cfg @@ -1,5 +1,6 @@ # Script from # https://www.suse.com/c/debugging-raspberry-pi-3-with-jtag/ +# with minor adaptions. transport select jtag