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@ -35,6 +35,7 @@ int amd_common_pre_reset(struct vendor_reset_dev *dev)
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return -ENOMEM;
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dev->vendor_private = priv;
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priv->vdev = dev;
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spin_lock_init(&priv->pcie_lock);
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spin_lock_init(&priv->reg_lock);
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@ -80,6 +81,9 @@ int amd_common_post_reset(struct vendor_reset_dev *dev)
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if (!dev->reset_ret)
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pci_set_power_state(pdev, PCI_D3hot);
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kzfree(priv);
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dev->vendor_private = NULL;
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return 0;
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}
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@ -96,7 +100,7 @@ int smum_send_msg_to_smc(struct amd_fake_dev *adev, uint16_t msg, uint32_t *resp
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--timeout)
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udelay(1);
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if ((ret = RREG32(mmMP1_SMN_C2PMSG_90)) != 0x1)
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pci_info(to_vendor_reset_dev(adev->private)->pdev, "SMU error 0x%x (line %d)\n",
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pci_info(adev->private->vdev->pdev, "SMU error 0x%x (line %d)\n",
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ret, __LINE__);
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mutex_unlock(&adev->private->smu_lock);
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