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@ -30,52 +30,52 @@ Place, Suite 330, Boston, MA 02111-1307 USA
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#define DRM_DEBUG(fmt, args...) pr_debug("vendor-reset-drm: " fmt, ##args)
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static inline bool drm_can_sleep(void)
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{
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if (in_atomic() || in_dbg_master() || irqs_disabled())
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return false;
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return true;
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if (in_atomic() || in_dbg_master() || irqs_disabled())
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return false;
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return true;
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}
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#define RREG32(reg) \
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({ \
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u32 __out; \
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if (((reg)*4) < adev_to_amd_private(adev)->mmio_size) \
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__out = readl(adev_to_amd_private(adev)->mmio + (reg)); \
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else \
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{ \
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writel(((reg)*4), adev_to_amd_private(adev)->mmio + mmMM_INDEX); \
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__out = readl(adev_to_amd_private(adev)->mmio + mmMM_DATA); \
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} \
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__out; \
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#define RREG32(reg) \
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({ \
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u32 __out; \
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if (((reg) * 4) < adev_to_amd_private(adev)->mmio_size) \
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__out = readl(adev_to_amd_private(adev)->mmio + (reg)); \
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else \
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{ \
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writel(((reg) * 4), adev_to_amd_private(adev)->mmio + mmMM_INDEX); \
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__out = readl(adev_to_amd_private(adev)->mmio + mmMM_DATA); \
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} \
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__out; \
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})
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#define WREG32(reg, v) \
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do \
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{ \
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if (((reg)*4) < adev_to_amd_private(adev)->mmio_size) \
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writel(v, adev_to_amd_private(adev)->mmio + (reg)); \
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else \
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{ \
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writel(((reg)*4), adev_to_amd_private(adev)->mmio + mmMM_INDEX); \
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writel(v, adev_to_amd_private(adev)->mmio + mmMM_DATA); \
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} \
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#define WREG32(reg, v) \
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do \
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{ \
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if (((reg) * 4) < adev_to_amd_private(adev)->mmio_size) \
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writel(v, adev_to_amd_private(adev)->mmio + (reg)); \
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else \
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{ \
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writel(((reg) * 4), adev_to_amd_private(adev)->mmio + mmMM_INDEX); \
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writel(v, adev_to_amd_private(adev)->mmio + mmMM_DATA); \
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} \
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} while (0)
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#define WREG32_PCIE(reg, v) \
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do \
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{ \
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WREG32(mmPCIE_INDEX2, reg); \
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(void)RREG32(mmPCIE_INDEX2); \
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WREG32(mmPCIE_DATA2, v); \
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(void)RREG32(mmPCIE_DATA2); \
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#define WREG32_PCIE(reg, v) \
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do \
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{ \
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WREG32(mmPCIE_INDEX2, reg); \
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(void)RREG32(mmPCIE_INDEX2); \
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WREG32(mmPCIE_DATA2, v); \
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(void)RREG32(mmPCIE_DATA2); \
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} while (0)
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#define RREG32_PCIE(reg) \
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({ \
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u32 __tmp_read; \
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WREG32(mmPCIE_INDEX2, reg); \
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(void)RREG32(mmPCIE_INDEX2); \
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__tmp_read = RREG32(mmPCIE_DATA2); \
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__tmp_read; \
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#define RREG32_PCIE(reg) \
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({ \
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u32 __tmp_read; \
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WREG32(mmPCIE_INDEX2, reg); \
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(void)RREG32(mmPCIE_INDEX2); \
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__tmp_read = RREG32(mmPCIE_DATA2); \
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__tmp_read; \
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})
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/* KIQ is only used for SRIOV accesses, we are not targetting these devices so
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@ -117,8 +117,6 @@ struct amd_vendor_private
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{
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u16 cfg;
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struct pci_dev *audio_pdev;
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struct vendor_reset_dev *vdev;
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struct pci_saved_state *saved_state;
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struct amd_fake_dev adev;
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