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81 lines
3.7 KiB
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81 lines
3.7 KiB
Markdown
# Tutorial 04 - Mailboxes
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The Raspberry Pi 3 also has a more powerful UART, `UART0`, that among other
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features, supports programmable clock rates. Before we can go on with setting
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up `UART0`, we need mailboxes. Mailboxes are an interface between the Pi's ARM
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CPU cores and the GPU. They will be used as a means to request work from the
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GPU, for example, requesting to program a certain clock for `UART0`.
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In this tutorial, we'll start slowly and use it to query the Raspberry's serial
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number and print that out on the already functional `UART1`.
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## uart.rs
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`MiniUart::hex(&self, d: u32)` prints out a binary value in hexadecimal format.
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## mbox.rs
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The mailbox interface. First we fill up the message in the `mbox.buffer` array,
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then we call `Mbox::call(&mut self, channel: u32)` to pass it to the GPU,
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specifying the mailbox channel. In this example we have used the [property
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channel], which requires the message to be formatted as:
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[property channel]: (https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface)
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```
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0. size of the message in bytes, (x+1)*4
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1. mbox::REQUEST magic value, indicates request message
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2-x. tags
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x+1. mbox::tag::LAST magic value, indicates no more tags
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```
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Where each tag looks like:
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```
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n+0. tag identifier
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n+1. value buffer size in bytes
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n+2. must be zero
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n+3. optional value buffer
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```
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### Synchronization
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When signaling the GPU about a new mailbox message, we need to take care that
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mailbox buffer setup has really finished. Both setting up mailbox contents and
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signaling the GPU is done with store operations to independent memory locations
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(RAM and MMIO). Since compilers are free to reorder instructions without
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control-flow or data-dependencies for optimization purposes, we need to take
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care that signaling the GPU really takes place _after_ all of the contents have
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been written to the mailbox buffer.
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One way to do this would be to define the whole mailbox buffer as `volatile`, as
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well as the location that we write to to signal the GPU. The compiler is not
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allowed to reorder memory operations tagged with the `volatile` keyword with
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each other. But this is not needed here. We don't care if the compiler optimizes
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the buffer setup code as long as signaling the GPU takes place afterwards.
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Therefore, we prevent premature signaling by inserting an explicit [compiler
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fence] after the buffer preparation code. Since we signal the CPU by calling
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another function, the fence would only be effective if that function was a)
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inlined and b) the inlined instructions then reordered with buffer setup
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code. Otherwise the compiler has to assume that the called function has
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dependencies on previous memory operations and not reorder here. Although there
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is little chance that the reordering scenario happens, I'll leave the fence
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there nonetheless for academic purposes :-)
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Please note that such reordering might also be done by CPUs that feature
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[out-of-order execution]. Lucky us, although the Rasperry Pi 3 features
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`ARMv8.0-A` CPU cores, the `Cortex-A53` variant is used, [which does not support
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this feature]. Otherwise, a [fence] that additionally [emits corresponding CPU
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instructions] to prevent this behavior would be needed.
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[compiler fence]: https://doc.rust-lang.org/beta/core/sync/atomic/fn.compiler_fence.html
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[out-of-order execution]: https://en.wikipedia.org/wiki/Out-of-order_execution
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[which does not support this feature]: https://en.wikipedia.org/wiki/Comparison_of_ARMv8-A_cores
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[fence]: https://doc.rust-lang.org/std/sync/atomic/fn.fence.html
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[emits corresponding CPU instructions]: https://developer.arm.com/products/architecture/a-profile/docs/100941/latest/barriers
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## main.rs
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We query the board's serial number and then we display it on the UART.
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