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74 lines
2.9 KiB
Markdown
74 lines
2.9 KiB
Markdown
# Tutorial 04 - Mailboxes
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Before we could go on with UART0, we need mailboxes. So in this tutorial we
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introduce the mailbox interface. We'll use it to query the board's serial
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number and print that out on UART1.
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NOTE: qemu does not redirect UART1 to terminal by default, only UART0!
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## uart.rs
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`MiniUart::hex(&self, d: u32)` prints out a binary value in hexadecimal format.
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## mbox.rs
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The mailbox interface. First we fill up the message in the `mbox.buffer` array,
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then we call `Mbox::call(&mut self, channel: u32)` to pass it to the GPU,
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specifying the mailbox channel. In this example we have used the [property
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channel], which requires the message to be formatted as:
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[property channel]: (https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface)
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```
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0. size of the message in bytes, (x+1)*4
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1. mbox::REQUEST magic value, indicates request message
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2-x. tags
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x+1. mbox::tag::LAST magic value, indicates no more tags
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```
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Where each tag looks like:
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```
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n+0. tag identifier
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n+1. value buffer size in bytes
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n+2. must be zero
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n+3. optional value buffer
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```
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### rlibc
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The mailbox buffer is a fixed array that is zero-initialized. To achieve
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zero-initialization, Rust utilizies and links to the `memset()` function, which
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is normally provided by `libc`.
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Since we are writing a `no_std` crate, we need to explicitly provide it. The
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easiest way is pulling in [rlibc] by adding it as an `extern crate` to `main.rs`
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and adding the dependency to `Cargo.toml`.
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[rlibc]: https://github.com/alexcrichton/rlibc
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### Synchronization
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When signaling the GPU about a new mailbox message, we need to take care that
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mailbox buffer setup has really finished. Both setting up mailbox contents and
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signaling the GPU is done with store operations to memory (RAM and MMIO). There
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is an unlikely chance that the compiler reorders instructions, resulting in
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signaling the GPU _before_ all of the contents have been written to the mailbox
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buffer. We prevent this by inserting a [compiler fence].
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Please note that such reordering might also be done by CPUs that feature
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[out-of-order execution]. Lucky us, although the Rasperry Pi 3 features
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`ARMv8.0-A` CPU cores, the `Cortex-A53` variant is used, [which does not support
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this feature]. Otherwise, a [fence] that additionally [emits corresponding CPU
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instructions] to prevent this behavior would be needed.
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[compiler fence]: https://doc.rust-lang.org/beta/core/sync/atomic/fn.compiler_fence.html
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[out-of-order execution]: https://en.wikipedia.org/wiki/Out-of-order_execution
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[which does not support this feature]: https://en.wikipedia.org/wiki/Comparison_of_ARMv8-A_cores
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[fence]: https://doc.rust-lang.org/std/sync/atomic/fn.fence.html
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[emits corresponding CPU instructions]: https://developer.arm.com/products/architecture/a-profile/docs/100941/latest/barriers
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## main.rs
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We query the board's serial number and then we display it on the serial console.
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