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@ -53,7 +53,7 @@ diff -uNr 03_hacky_hello_world/src/_arch/aarch64/cpu/smp.rs 04_zero_overhead_abs
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diff -uNr 03_hacky_hello_world/src/_arch/aarch64/cpu.rs 04_zero_overhead_abstraction/src/_arch/aarch64/cpu.rs
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diff -uNr 03_hacky_hello_world/src/_arch/aarch64/cpu.rs 04_zero_overhead_abstraction/src/_arch/aarch64/cpu.rs
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--- 03_hacky_hello_world/src/_arch/aarch64/cpu.rs
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--- 03_hacky_hello_world/src/_arch/aarch64/cpu.rs
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+++ 04_zero_overhead_abstraction/src/_arch/aarch64/cpu.rs
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+++ 04_zero_overhead_abstraction/src/_arch/aarch64/cpu.rs
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@@ -4,8 +4,35 @@
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@@ -4,8 +4,34 @@
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//! Architectural processor code.
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//! Architectural processor code.
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@ -79,7 +79,6 @@ diff -uNr 03_hacky_hello_world/src/_arch/aarch64/cpu.rs 04_zero_overhead_abstrac
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+pub unsafe fn _start() -> ! {
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+pub unsafe fn _start() -> ! {
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+ use crate::runtime_init;
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+ use crate::runtime_init;
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+
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+
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+ // Expect the boot core to start in EL2.
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+ if bsp::cpu::BOOT_CORE_ID == cpu::smp::core_id() {
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+ if bsp::cpu::BOOT_CORE_ID == cpu::smp::core_id() {
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+ SP.set(bsp::memory::boot_core_stack_end() as u64);
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+ SP.set(bsp::memory::boot_core_stack_end() as u64);
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+ runtime_init::runtime_init()
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+ runtime_init::runtime_init()
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@ -91,7 +90,7 @@ diff -uNr 03_hacky_hello_world/src/_arch/aarch64/cpu.rs 04_zero_overhead_abstrac
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//--------------------------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------------------------
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// Public Code
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// Public Code
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@@ -14,13 +41,7 @@
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@@ -14,13 +40,7 @@
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/// Pause execution on the core.
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/// Pause execution on the core.
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#[inline(always)]
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#[inline(always)]
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pub fn wait_forever() -> ! {
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pub fn wait_forever() -> ! {
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