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@ -242,13 +242,13 @@ impl exception::asynchronous::interface::IRQHandler for PL011Uart {
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fn handle(&self) -> Result<(), &'static str> {
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let mut r = &self.inner;
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r.lock(|inner| {
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let pending = inner.RIS.extract();
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let pending = inner.MIS.extract();
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// Clear all pending IRQs.
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inner.ICR.write(ICR::ALL::CLEAR);
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// Check for any kind of RX interrupt.
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if pending.matches_any(RIS::RXRIS::SET + RIS::RTRIS::SET) {
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if pending.matches_any(MIS::RXMIS::SET + MIS::RTMIS::SET) {
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// Echo any received characters.
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while let Some(c) = inner.read_char_converting(BlockingMode::NonBlocking) {
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inner.write_char(c)
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@ -1857,7 +1857,7 @@ diff -uNr 13_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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use core::{fmt, ops};
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use register::{mmio::*, register_bitfields, register_structs};
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@@ -106,6 +108,47 @@
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@@ -106,6 +108,48 @@
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]
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],
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@ -1876,9 +1876,9 @@ diff -uNr 13_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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+
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+ /// Interrupt Mask Set Clear Register
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+ IMSC [
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+ // Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR
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+ // interrupt. On a write of 1, the mask of the interrupt is set. A write of 0 clears the
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+ // mask.
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+ /// Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR
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+ /// interrupt. On a write of 1, the mask of the interrupt is set. A write of 0 clears the
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+ /// mask.
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+ RTIM OFFSET(6) NUMBITS(1) [
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+ Disabled = 0,
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+ Enabled = 1
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@ -1892,20 +1892,21 @@ diff -uNr 13_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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+ ]
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+ ],
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+
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+ /// Raw Interrupt Status Register
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+ RIS [
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+ // Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR
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+ // interrupt.
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+ RTRIS OFFSET(6) NUMBITS(1) [],
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+ /// Masked Interrupt Status Register
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+ MIS [
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+ /// Receive timeout masked interrupt status. Returns the masked interrupt state of the
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+ /// UARTRTINTR interrupt.
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+ RTMIS OFFSET(6) NUMBITS(1) [],
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+
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+ /// Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt.
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+ RXRIS OFFSET(4) NUMBITS(1) []
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+ /// Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR
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+ /// interrupt.
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+ RXMIS OFFSET(4) NUMBITS(1) []
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+ ],
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+
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/// Interrupt Clear Register
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ICR [
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/// Meta field for all pending interrupts
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@@ -113,6 +156,12 @@
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@@ -113,6 +157,12 @@
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]
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}
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@ -1918,18 +1919,19 @@ diff -uNr 13_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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//--------------------------------------------------------------------------------------------------
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// Public Definitions
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//--------------------------------------------------------------------------------------------------
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@@ -128,7 +177,9 @@
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@@ -128,7 +178,10 @@
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(0x28 => FBRD: WriteOnly<u32, FBRD::Register>),
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(0x2c => LCRH: WriteOnly<u32, LCRH::Register>),
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(0x30 => CR: WriteOnly<u32, CR::Register>),
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- (0x34 => _reserved3),
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+ (0x34 => IFLS: ReadWrite<u32, IFLS::Register>),
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+ (0x38 => IMSC: ReadWrite<u32, IMSC::Register>),
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+ (0x3C => RIS: ReadWrite<u32, RIS::Register>),
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+ (0x3C => _reserved3),
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+ (0x40 => MIS: ReadOnly<u32, MIS::Register>),
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(0x44 => ICR: WriteOnly<u32, ICR::Register>),
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(0x48 => @END),
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}
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@@ -145,7 +196,8 @@
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@@ -145,7 +198,8 @@
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/// Representation of the UART.
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pub struct PL011Uart {
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@ -1939,7 +1941,7 @@ diff -uNr 13_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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}
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//--------------------------------------------------------------------------------------------------
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@@ -197,6 +249,8 @@
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@@ -197,6 +251,8 @@
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self.FBRD.write(FBRD::FBRD.val(2));
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self.LCRH
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.write(LCRH::WLEN::EightBit + LCRH::FEN::FifosEnabled); // 8N1 + Fifo on
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@ -1948,7 +1950,7 @@ diff -uNr 13_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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self.CR
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.write(CR::UARTEN::Enabled + CR::TXE::Enabled + CR::RXE::Enabled);
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}
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@@ -218,6 +272,35 @@
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@@ -218,6 +274,35 @@
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self.chars_written += 1;
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}
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@ -1984,7 +1986,7 @@ diff -uNr 13_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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}
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/// Implementing `core::fmt::Write` enables usage of the `format_args!` macros, which in turn are
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@@ -243,9 +326,10 @@
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@@ -243,9 +328,10 @@
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/// # Safety
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///
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/// - The user must ensure to provide the correct `base_addr`.
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@ -1997,7 +1999,7 @@ diff -uNr 13_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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}
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}
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}
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@@ -266,6 +350,21 @@
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@@ -266,6 +352,21 @@
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Ok(())
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}
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@ -2019,7 +2021,7 @@ diff -uNr 13_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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}
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impl console::interface::Write for PL011Uart {
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@@ -297,25 +396,7 @@
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@@ -297,25 +398,7 @@
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impl console::interface::Read for PL011Uart {
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fn read_char(&self) -> char {
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let mut r = &self.inner;
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@ -2046,7 +2048,7 @@ diff -uNr 13_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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}
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fn clear(&self) {
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@@ -340,3 +421,25 @@
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@@ -340,3 +423,25 @@
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r.lock(|inner| inner.chars_read)
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}
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}
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@ -2055,13 +2057,13 @@ diff -uNr 13_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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+ fn handle(&self) -> Result<(), &'static str> {
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+ let mut r = &self.inner;
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+ r.lock(|inner| {
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+ let pending = inner.RIS.extract();
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+ let pending = inner.MIS.extract();
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+
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+ // Clear all pending IRQs.
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+ inner.ICR.write(ICR::ALL::CLEAR);
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+
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+ // Check for any kind of RX interrupt.
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+ if pending.matches_any(RIS::RXRIS::SET + RIS::RTRIS::SET) {
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+ if pending.matches_any(MIS::RXMIS::SET + MIS::RTMIS::SET) {
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+ // Echo any received characters.
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+ while let Some(c) = inner.read_char_converting(BlockingMode::NonBlocking) {
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+ inner.write_char(c)
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