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@ -26,6 +26,47 @@ Place, Suite 330, Boston, MA 02111-1307 USA
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#include "firmware.h"
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#define to_adev(info) ((struct amd_fake_dev *)container_of(info, struct amd_fake_dev, card_info))
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#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
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#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
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/**
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* amdgpu_io_rreg - read an IO register
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*
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* @adev: amdgpu_device pointer
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* @reg: dword aligned register offset
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*
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* Returns the 32 bit value from the offset specified.
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*/
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u32 amdgpu_io_rreg(struct amd_fake_dev *adev, u32 reg)
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{
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if ((reg * 4) < adev_to_amd_private(adev)->rio_mem_size)
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return ioread32(adev_to_amd_private(adev)->rio_mem + (reg * 4));
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else
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{
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iowrite32((reg * 4), adev_to_amd_private(adev)->rio_mem + (mmMM_INDEX * 4));
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return ioread32(adev_to_amd_private(adev)->rio_mem + (mmMM_DATA * 4));
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}
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}
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/**
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* amdgpu_io_wreg - write to an IO register
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*
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* @adev: amdgpu_device pointer
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* @reg: dword aligned register offset
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* @v: 32 bit value to write to the register
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*
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* Writes the value specified to the offset specified.
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*/
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void amdgpu_io_wreg(struct amd_fake_dev *adev, u32 reg, u32 v)
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{
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if ((reg * 4) < adev_to_amd_private(adev)->rio_mem_size)
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iowrite32(v, adev_to_amd_private(adev)->rio_mem + (reg * 4));
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else
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{
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iowrite32((reg * 4), adev_to_amd_private(adev)->rio_mem + (mmMM_INDEX * 4));
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iowrite32(v, adev_to_amd_private(adev)->rio_mem + (mmMM_DATA * 4));
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}
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}
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static uint32_t null_read(struct card_info *info, uint32_t reg)
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{
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@ -52,6 +93,22 @@ static uint32_t reg_read(struct card_info *info, uint32_t reg)
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return r;
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}
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static uint32_t ioreg_read(struct card_info *info, uint32_t reg)
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{
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struct amd_fake_dev *adev = to_adev(info);
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uint32_t r;
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r = RREG32_IO(reg);
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return r;
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}
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static void ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
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{
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struct amd_fake_dev *adev = to_adev(info);
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WREG32_IO(reg, val);
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}
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int atom_bios_init(struct amd_fake_dev *adev)
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{
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struct card_info *info = &adev->card_info;
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@ -59,8 +116,19 @@ int atom_bios_init(struct amd_fake_dev *adev)
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info->mc_read = info->pll_read = null_read;
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info->mc_write = info->pll_write = null_write;
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info->reg_read = info->ioreg_read = reg_read;
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info->reg_write = info->ioreg_write = reg_write;
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info->reg_read = reg_read;
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info->reg_write = reg_write;
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if (adev_to_amd_private(adev)->rio_mem)
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{
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info->ioreg_read = ioreg_read;
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info->ioreg_write = ioreg_write;
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}
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else
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{
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pr_warn("vendor-reset: using MMIO to access I/O\n");
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info->ioreg_read = reg_read;
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info->ioreg_write = reg_write;
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}
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adev->atom_context = amdgpu_atom_parse(info, adev->bios);
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if (!adev->atom_context)
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