mirror of https://github.com/gnif/vendor-reset
Load and parse BIOS/firmware where possible
Adam Madsen
4 years ago
parent
7c1c9aa44a
commit
68ca4816b6
@ -0,0 +1,744 @@
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/*
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* Copyright 2006-2007 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/* based on stg/asic_reg/drivers/inc/asic_reg/ObjectID.h ver 23 */
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#ifndef _OBJECTID_H
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#define _OBJECTID_H
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#if defined(_X86_)
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#pragma pack(1)
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#endif
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/****************************************************/
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/* Graphics Object Type Definition */
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/****************************************************/
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#define GRAPH_OBJECT_TYPE_NONE 0x0
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#define GRAPH_OBJECT_TYPE_GPU 0x1
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#define GRAPH_OBJECT_TYPE_ENCODER 0x2
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#define GRAPH_OBJECT_TYPE_CONNECTOR 0x3
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#define GRAPH_OBJECT_TYPE_ROUTER 0x4
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/* deleted */
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#define GRAPH_OBJECT_TYPE_DISPLAY_PATH 0x6
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#define GRAPH_OBJECT_TYPE_GENERIC 0x7
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/****************************************************/
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/* Encoder Object ID Definition */
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/****************************************************/
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#define ENCODER_OBJECT_ID_NONE 0x00
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/* Radeon Class Display Hardware */
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#define ENCODER_OBJECT_ID_INTERNAL_LVDS 0x01
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#define ENCODER_OBJECT_ID_INTERNAL_TMDS1 0x02
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#define ENCODER_OBJECT_ID_INTERNAL_TMDS2 0x03
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#define ENCODER_OBJECT_ID_INTERNAL_DAC1 0x04
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#define ENCODER_OBJECT_ID_INTERNAL_DAC2 0x05 /* TV/CV DAC */
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#define ENCODER_OBJECT_ID_INTERNAL_SDVOA 0x06
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#define ENCODER_OBJECT_ID_INTERNAL_SDVOB 0x07
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/* External Third Party Encoders */
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#define ENCODER_OBJECT_ID_SI170B 0x08
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#define ENCODER_OBJECT_ID_CH7303 0x09
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#define ENCODER_OBJECT_ID_CH7301 0x0A
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#define ENCODER_OBJECT_ID_INTERNAL_DVO1 0x0B /* This belongs to Radeon Class Display Hardware */
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#define ENCODER_OBJECT_ID_EXTERNAL_SDVOA 0x0C
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#define ENCODER_OBJECT_ID_EXTERNAL_SDVOB 0x0D
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#define ENCODER_OBJECT_ID_TITFP513 0x0E
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#define ENCODER_OBJECT_ID_INTERNAL_LVTM1 0x0F /* not used for Radeon */
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#define ENCODER_OBJECT_ID_VT1623 0x10
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#define ENCODER_OBJECT_ID_HDMI_SI1930 0x11
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#define ENCODER_OBJECT_ID_HDMI_INTERNAL 0x12
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#define ENCODER_OBJECT_ID_ALMOND 0x22
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#define ENCODER_OBJECT_ID_TRAVIS 0x23
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#define ENCODER_OBJECT_ID_NUTMEG 0x22
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#define ENCODER_OBJECT_ID_HDMI_ANX9805 0x26
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/* Kaleidoscope (KLDSCP) Class Display Hardware (internal) */
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#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 0x13
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#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 0x14
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#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 0x15
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#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 0x16 /* Shared with CV/TV and CRT */
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#define ENCODER_OBJECT_ID_SI178 0X17 /* External TMDS (dual link, no HDCP.) */
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#define ENCODER_OBJECT_ID_MVPU_FPGA 0x18 /* MVPU FPGA chip */
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#define ENCODER_OBJECT_ID_INTERNAL_DDI 0x19
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#define ENCODER_OBJECT_ID_VT1625 0x1A
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#define ENCODER_OBJECT_ID_HDMI_SI1932 0x1B
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#define ENCODER_OBJECT_ID_DP_AN9801 0x1C
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#define ENCODER_OBJECT_ID_DP_DP501 0x1D
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#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY 0x1E
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#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA 0x1F
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#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 0x20
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#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 0x21
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#define ENCODER_OBJECT_ID_INTERNAL_VCE 0x24
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#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY3 0x25
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#define ENCODER_OBJECT_ID_INTERNAL_AMCLK 0x27
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#define ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO 0xFF
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/****************************************************/
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/* Connector Object ID Definition */
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/****************************************************/
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#define CONNECTOR_OBJECT_ID_NONE 0x00
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#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I 0x01
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#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I 0x02
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#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 0x03
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#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D 0x04
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#define CONNECTOR_OBJECT_ID_VGA 0x05
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#define CONNECTOR_OBJECT_ID_COMPOSITE 0x06
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#define CONNECTOR_OBJECT_ID_SVIDEO 0x07
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#define CONNECTOR_OBJECT_ID_YPbPr 0x08
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#define CONNECTOR_OBJECT_ID_D_CONNECTOR 0x09
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#define CONNECTOR_OBJECT_ID_9PIN_DIN 0x0A /* Supports both CV & TV */
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#define CONNECTOR_OBJECT_ID_SCART 0x0B
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#define CONNECTOR_OBJECT_ID_HDMI_TYPE_A 0x0C
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#define CONNECTOR_OBJECT_ID_HDMI_TYPE_B 0x0D
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#define CONNECTOR_OBJECT_ID_LVDS 0x0E
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#define CONNECTOR_OBJECT_ID_7PIN_DIN 0x0F
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#define CONNECTOR_OBJECT_ID_PCIE_CONNECTOR 0x10
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#define CONNECTOR_OBJECT_ID_CROSSFIRE 0x11
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#define CONNECTOR_OBJECT_ID_HARDCODE_DVI 0x12
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#define CONNECTOR_OBJECT_ID_DISPLAYPORT 0x13
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#define CONNECTOR_OBJECT_ID_eDP 0x14
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#define CONNECTOR_OBJECT_ID_MXM 0x15
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#define CONNECTOR_OBJECT_ID_LVDS_eDP 0x16
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/* deleted */
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/****************************************************/
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/* Router Object ID Definition */
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/****************************************************/
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#define ROUTER_OBJECT_ID_NONE 0x00
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#define ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL 0x01
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/****************************************************/
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/* Generic Object ID Definition */
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/****************************************************/
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#define GENERIC_OBJECT_ID_NONE 0x00
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#define GENERIC_OBJECT_ID_GLSYNC 0x01
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#define GENERIC_OBJECT_ID_PX2_NON_DRIVABLE 0x02
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#define GENERIC_OBJECT_ID_MXM_OPM 0x03
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#define GENERIC_OBJECT_ID_STEREO_PIN 0x04 //This object could show up from Misc Object table, it follows ATOM_OBJECT format, and contains one ATOM_OBJECT_GPIO_CNTL_RECORD for the stereo pin
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#define GENERIC_OBJECT_ID_BRACKET_LAYOUT 0x05
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/****************************************************/
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/* Graphics Object ENUM ID Definition */
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/****************************************************/
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#define GRAPH_OBJECT_ENUM_ID1 0x01
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#define GRAPH_OBJECT_ENUM_ID2 0x02
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#define GRAPH_OBJECT_ENUM_ID3 0x03
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#define GRAPH_OBJECT_ENUM_ID4 0x04
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#define GRAPH_OBJECT_ENUM_ID5 0x05
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#define GRAPH_OBJECT_ENUM_ID6 0x06
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#define GRAPH_OBJECT_ENUM_ID7 0x07
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/****************************************************/
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/* Graphics Object ID Bit definition */
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/****************************************************/
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#define OBJECT_ID_MASK 0x00FF
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#define ENUM_ID_MASK 0x0700
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#define RESERVED1_ID_MASK 0x0800
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#define OBJECT_TYPE_MASK 0x7000
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#define RESERVED2_ID_MASK 0x8000
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#define OBJECT_ID_SHIFT 0x00
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#define ENUM_ID_SHIFT 0x08
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#define OBJECT_TYPE_SHIFT 0x0C
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/****************************************************/
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/* Graphics Object family definition */
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/****************************************************/
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#define CONSTRUCTOBJECTFAMILYID(GRAPHICS_OBJECT_TYPE, GRAPHICS_OBJECT_ID) (GRAPHICS_OBJECT_TYPE << OBJECT_TYPE_SHIFT | \
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GRAPHICS_OBJECT_ID << OBJECT_ID_SHIFT)
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/****************************************************/
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/* GPU Object ID definition - Shared with BIOS */
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/****************************************************/
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#define GPU_ENUM_ID1 ( GRAPH_OBJECT_TYPE_GPU << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT)
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/****************************************************/
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/* Encoder Object ID definition - Shared with BIOS */
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/****************************************************/
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/*
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#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101
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#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 0x2102
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#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 0x2103
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#define ENCODER_INTERNAL_DAC1_ENUM_ID1 0x2104
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#define ENCODER_INTERNAL_DAC2_ENUM_ID1 0x2105
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#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 0x2106
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#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 0x2107
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#define ENCODER_SIL170B_ENUM_ID1 0x2108
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#define ENCODER_CH7303_ENUM_ID1 0x2109
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#define ENCODER_CH7301_ENUM_ID1 0x210A
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#define ENCODER_INTERNAL_DVO1_ENUM_ID1 0x210B
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#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1 0x210C
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#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1 0x210D
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#define ENCODER_TITFP513_ENUM_ID1 0x210E
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#define ENCODER_INTERNAL_LVTM1_ENUM_ID1 0x210F
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#define ENCODER_VT1623_ENUM_ID1 0x2110
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#define ENCODER_HDMI_SI1930_ENUM_ID1 0x2111
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#define ENCODER_HDMI_INTERNAL_ENUM_ID1 0x2112
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#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 0x2113
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#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 0x2114
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#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 0x2115
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#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116
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#define ENCODER_SI178_ENUM_ID1 0x2117
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#define ENCODER_MVPU_FPGA_ENUM_ID1 0x2118
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#define ENCODER_INTERNAL_DDI_ENUM_ID1 0x2119
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#define ENCODER_VT1625_ENUM_ID1 0x211A
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#define ENCODER_HDMI_SI1932_ENUM_ID1 0x211B
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#define ENCODER_ENCODER_DP_AN9801_ENUM_ID1 0x211C
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#define ENCODER_DP_DP501_ENUM_ID1 0x211D
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#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1 0x211E
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*/
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#define ENCODER_INTERNAL_LVDS_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_INTERNAL_LVDS << OBJECT_ID_SHIFT)
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#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_INTERNAL_TMDS1 << OBJECT_ID_SHIFT)
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#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_INTERNAL_TMDS2 << OBJECT_ID_SHIFT)
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#define ENCODER_INTERNAL_DAC1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_INTERNAL_DAC1 << OBJECT_ID_SHIFT)
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#define ENCODER_INTERNAL_DAC2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_INTERNAL_DAC2 << OBJECT_ID_SHIFT)
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#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT)
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#define ENCODER_INTERNAL_SDVOA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT)
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#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_INTERNAL_SDVOB << OBJECT_ID_SHIFT)
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#define ENCODER_SIL170B_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_SI170B << OBJECT_ID_SHIFT)
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#define ENCODER_CH7303_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_CH7303 << OBJECT_ID_SHIFT)
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#define ENCODER_CH7301_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_CH7301 << OBJECT_ID_SHIFT)
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#define ENCODER_INTERNAL_DVO1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_INTERNAL_DVO1 << OBJECT_ID_SHIFT)
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#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT)
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#define ENCODER_EXTERNAL_SDVOA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT)
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#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_EXTERNAL_SDVOB << OBJECT_ID_SHIFT)
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#define ENCODER_TITFP513_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_TITFP513 << OBJECT_ID_SHIFT)
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#define ENCODER_INTERNAL_LVTM1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_INTERNAL_LVTM1 << OBJECT_ID_SHIFT)
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#define ENCODER_VT1623_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_VT1623 << OBJECT_ID_SHIFT)
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#define ENCODER_HDMI_SI1930_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_HDMI_SI1930 << OBJECT_ID_SHIFT)
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#define ENCODER_HDMI_INTERNAL_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_HDMI_INTERNAL << OBJECT_ID_SHIFT)
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#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT)
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#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT)
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#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 << OBJECT_ID_SHIFT)
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#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 << OBJECT_ID_SHIFT)
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#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 << OBJECT_ID_SHIFT) // Shared with CV/TV and CRT
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#define ENCODER_SI178_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT)
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#define ENCODER_MVPU_FPGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_MVPU_FPGA << OBJECT_ID_SHIFT)
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#define ENCODER_INTERNAL_DDI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT)
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|
||||
#define ENCODER_VT1625_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
ENCODER_OBJECT_ID_VT1625 << OBJECT_ID_SHIFT)
|
||||
|
||||
#define ENCODER_HDMI_SI1932_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
ENCODER_OBJECT_ID_HDMI_SI1932 << OBJECT_ID_SHIFT)
|
||||
|
||||
#define ENCODER_DP_DP501_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
ENCODER_OBJECT_ID_DP_DP501 << OBJECT_ID_SHIFT)
|
||||
|
||||
#define ENCODER_DP_AN9801_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
ENCODER_OBJECT_ID_DP_AN9801 << OBJECT_ID_SHIFT)
|
||||
|
||||
#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT)
|
||||
|
||||
#define ENCODER_INTERNAL_UNIPHY_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
|
||||
ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT)
|
||||
|
||||
#define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)
|
||||
|
||||
#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT)
|
||||
|
||||
#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
|
||||
ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT)
|
||||
|
||||
#define ENCODER_INTERNAL_UNIPHY2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT)
|
||||
|
||||
#define ENCODER_INTERNAL_UNIPHY2_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
|
||||
ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT)
|
||||
|
||||
#define ENCODER_INTERNAL_UNIPHY3_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
ENCODER_OBJECT_ID_INTERNAL_UNIPHY3 << OBJECT_ID_SHIFT)
|
||||
|
||||
#define ENCODER_INTERNAL_UNIPHY3_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
|
||||
ENCODER_OBJECT_ID_INTERNAL_UNIPHY3 << OBJECT_ID_SHIFT)
|
||||
|
||||
#define ENCODER_GENERAL_EXTERNAL_DVO_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO << OBJECT_ID_SHIFT)
|
||||
|
||||
#define ENCODER_ALMOND_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
ENCODER_OBJECT_ID_ALMOND << OBJECT_ID_SHIFT)
|
||||
|
||||
#define ENCODER_ALMOND_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
|
||||
ENCODER_OBJECT_ID_ALMOND << OBJECT_ID_SHIFT)
|
||||
|
||||
#define ENCODER_TRAVIS_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
ENCODER_OBJECT_ID_TRAVIS << OBJECT_ID_SHIFT)
|
||||
|
||||
#define ENCODER_TRAVIS_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
|
||||
ENCODER_OBJECT_ID_TRAVIS << OBJECT_ID_SHIFT)
|
||||
|
||||
#define ENCODER_NUTMEG_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
ENCODER_OBJECT_ID_NUTMEG << OBJECT_ID_SHIFT)
|
||||
|
||||
#define ENCODER_VCE_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
ENCODER_OBJECT_ID_INTERNAL_VCE << OBJECT_ID_SHIFT)
|
||||
|
||||
#define ENCODER_HDMI_ANX9805_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
ENCODER_OBJECT_ID_HDMI_ANX9805 << OBJECT_ID_SHIFT)
|
||||
|
||||
/****************************************************/
|
||||
/* Connector Object ID definition - Shared with BIOS */
|
||||
/****************************************************/
|
||||
/*
|
||||
#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1 0x3101
|
||||
#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1 0x3102
|
||||
#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1 0x3103
|
||||
#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 0x3104
|
||||
#define CONNECTOR_VGA_ENUM_ID1 0x3105
|
||||
#define CONNECTOR_COMPOSITE_ENUM_ID1 0x3106
|
||||
#define CONNECTOR_SVIDEO_ENUM_ID1 0x3107
|
||||
#define CONNECTOR_YPbPr_ENUM_ID1 0x3108
|
||||
#define CONNECTOR_D_CONNECTORE_ENUM_ID1 0x3109
|
||||
#define CONNECTOR_9PIN_DIN_ENUM_ID1 0x310A
|
||||
#define CONNECTOR_SCART_ENUM_ID1 0x310B
|
||||
#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1 0x310C
|
||||
#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1 0x310D
|
||||
#define CONNECTOR_LVDS_ENUM_ID1 0x310E
|
||||
#define CONNECTOR_7PIN_DIN_ENUM_ID1 0x310F
|
||||
#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 0x3110
|
||||
*/
|
||||
#define CONNECTOR_LVDS_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_LVDS_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_eDP_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_eDP << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_eDP_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_eDP << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID3 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID4 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID5 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID5 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID6 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID6 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID3 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID4 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_VGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_VGA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_COMPOSITE_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_COMPOSITE_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_SVIDEO_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_SVIDEO_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_YPbPr_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_YPbPr_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_D_CONNECTOR_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_D_CONNECTOR_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_9PIN_DIN_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_9PIN_DIN_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_SCART_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_SCART_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_HDMI_TYPE_A_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_HDMI_TYPE_A_ENUM_ID3 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_HDMI_TYPE_A_ENUM_ID4 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_HDMI_TYPE_A_ENUM_ID5 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID5 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_HDMI_TYPE_A_ENUM_ID6 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID6 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_HDMI_TYPE_B_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_7PIN_DIN_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_7PIN_DIN_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_CROSSFIRE_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_CROSSFIRE_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT)
|
||||
|
||||
|
||||
#define CONNECTOR_HARDCODE_DVI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_HARDCODE_DVI_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_DISPLAYPORT_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_DISPLAYPORT_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_DISPLAYPORT_ENUM_ID3 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_DISPLAYPORT_ENUM_ID4 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_DISPLAYPORT_ENUM_ID5 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID5 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_DISPLAYPORT_ENUM_ID6 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID6 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_MXM_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DP_A
|
||||
|
||||
#define CONNECTOR_MXM_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DP_B
|
||||
|
||||
#define CONNECTOR_MXM_ENUM_ID3 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DP_C
|
||||
|
||||
#define CONNECTOR_MXM_ENUM_ID4 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DP_D
|
||||
|
||||
#define CONNECTOR_MXM_ENUM_ID5 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID5 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_LVDS_TXxx
|
||||
|
||||
#define CONNECTOR_MXM_ENUM_ID6 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID6 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_LVDS_UXxx
|
||||
|
||||
#define CONNECTOR_MXM_ENUM_ID7 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID7 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DAC
|
||||
|
||||
#define CONNECTOR_LVDS_eDP_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_LVDS_eDP << OBJECT_ID_SHIFT)
|
||||
|
||||
#define CONNECTOR_LVDS_eDP_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
|
||||
CONNECTOR_OBJECT_ID_LVDS_eDP << OBJECT_ID_SHIFT)
|
||||
|
||||
/****************************************************/
|
||||
/* Router Object ID definition - Shared with BIOS */
|
||||
/****************************************************/
|
||||
#define ROUTER_I2C_EXTENDER_CNTL_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ROUTER << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL << OBJECT_ID_SHIFT)
|
||||
|
||||
/* deleted */
|
||||
|
||||
/****************************************************/
|
||||
/* Generic Object ID definition - Shared with BIOS */
|
||||
/****************************************************/
|
||||
#define GENERICOBJECT_GLSYNC_ENUM_ID1 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
GENERIC_OBJECT_ID_GLSYNC << OBJECT_ID_SHIFT)
|
||||
|
||||
#define GENERICOBJECT_PX2_NON_DRIVABLE_ID1 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
GENERIC_OBJECT_ID_PX2_NON_DRIVABLE<< OBJECT_ID_SHIFT)
|
||||
|
||||
#define GENERICOBJECT_PX2_NON_DRIVABLE_ID2 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
|
||||
GENERIC_OBJECT_ID_PX2_NON_DRIVABLE<< OBJECT_ID_SHIFT)
|
||||
|
||||
#define GENERICOBJECT_MXM_OPM_ENUM_ID1 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
GENERIC_OBJECT_ID_MXM_OPM << OBJECT_ID_SHIFT)
|
||||
|
||||
#define GENERICOBJECT_STEREO_PIN_ENUM_ID1 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
GENERIC_OBJECT_ID_STEREO_PIN << OBJECT_ID_SHIFT)
|
||||
|
||||
#define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT)
|
||||
|
||||
#define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
|
||||
GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT)
|
||||
/****************************************************/
|
||||
/* Object Cap definition - Shared with BIOS */
|
||||
/****************************************************/
|
||||
#define GRAPHICS_OBJECT_CAP_I2C 0x00000001L
|
||||
#define GRAPHICS_OBJECT_CAP_TABLE_ID 0x00000002L
|
||||
|
||||
|
||||
#define GRAPHICS_OBJECT_I2CCOMMAND_TABLE_ID 0x01
|
||||
#define GRAPHICS_OBJECT_HOTPLUGDETECTIONINTERUPT_TABLE_ID 0x02
|
||||
#define GRAPHICS_OBJECT_ENCODER_OUTPUT_PROTECTION_TABLE_ID 0x03
|
||||
|
||||
#if defined(_X86_)
|
||||
#pragma pack()
|
||||
#endif
|
||||
|
||||
#endif /*GRAPHICTYPE */
|
||||
|
||||
|
||||
|
||||
|
||||
@ -0,0 +1,240 @@
|
||||
/*
|
||||
* Copyright 2014 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __AMDGPU_ATOMBIOS_H__
|
||||
#define __AMDGPU_ATOMBIOS_H__
|
||||
|
||||
#include <kernel/types.h>
|
||||
|
||||
struct atom_clock_dividers
|
||||
{
|
||||
u32 post_div;
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
#ifdef __BIG_ENDIAN
|
||||
u32 reserved : 6;
|
||||
u32 whole_fb_div : 12;
|
||||
u32 frac_fb_div : 14;
|
||||
#else
|
||||
u32 frac_fb_div : 14;
|
||||
u32 whole_fb_div : 12;
|
||||
u32 reserved : 6;
|
||||
#endif
|
||||
};
|
||||
u32 fb_div;
|
||||
};
|
||||
u32 ref_div;
|
||||
bool enable_post_div;
|
||||
bool enable_dithen;
|
||||
u32 vco_mode;
|
||||
u32 real_clock;
|
||||
/* added for CI */
|
||||
u32 post_divider;
|
||||
u32 flags;
|
||||
};
|
||||
|
||||
struct atom_mpll_param
|
||||
{
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
#ifdef __BIG_ENDIAN
|
||||
u32 reserved : 8;
|
||||
u32 clkfrac : 12;
|
||||
u32 clkf : 12;
|
||||
#else
|
||||
u32 clkf : 12;
|
||||
u32 clkfrac : 12;
|
||||
u32 reserved : 8;
|
||||
#endif
|
||||
};
|
||||
u32 fb_div;
|
||||
};
|
||||
u32 post_div;
|
||||
u32 bwcntl;
|
||||
u32 dll_speed;
|
||||
u32 vco_mode;
|
||||
u32 yclk_sel;
|
||||
u32 qdr;
|
||||
u32 half_rate;
|
||||
};
|
||||
|
||||
#define MEM_TYPE_GDDR5 0x50
|
||||
#define MEM_TYPE_GDDR4 0x40
|
||||
#define MEM_TYPE_GDDR3 0x30
|
||||
#define MEM_TYPE_DDR2 0x20
|
||||
#define MEM_TYPE_GDDR1 0x10
|
||||
#define MEM_TYPE_DDR3 0xb0
|
||||
#define MEM_TYPE_MASK 0xf0
|
||||
|
||||
struct atom_memory_info
|
||||
{
|
||||
u8 mem_vendor;
|
||||
u8 mem_type;
|
||||
};
|
||||
|
||||
#define MAX_AC_TIMING_ENTRIES 16
|
||||
|
||||
struct atom_memory_clock_range_table
|
||||
{
|
||||
u8 num_entries;
|
||||
u8 rsv[3];
|
||||
u32 mclk[MAX_AC_TIMING_ENTRIES];
|
||||
};
|
||||
|
||||
#define VBIOS_MC_REGISTER_ARRAY_SIZE 32
|
||||
#define VBIOS_MAX_AC_TIMING_ENTRIES 20
|
||||
|
||||
struct atom_mc_reg_entry
|
||||
{
|
||||
u32 mclk_max;
|
||||
u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
|
||||
};
|
||||
|
||||
struct atom_mc_register_address
|
||||
{
|
||||
u16 s1;
|
||||
u8 pre_reg_data;
|
||||
};
|
||||
|
||||
struct atom_mc_reg_table
|
||||
{
|
||||
u8 last;
|
||||
u8 num_entries;
|
||||
struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
|
||||
struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
|
||||
};
|
||||
|
||||
#define MAX_VOLTAGE_ENTRIES 32
|
||||
|
||||
struct atom_voltage_table_entry
|
||||
{
|
||||
u16 value;
|
||||
u32 smio_low;
|
||||
};
|
||||
|
||||
struct atom_voltage_table
|
||||
{
|
||||
u32 count;
|
||||
u32 mask_low;
|
||||
u32 phase_delay;
|
||||
struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES];
|
||||
};
|
||||
|
||||
struct amdgpu_gpio_rec
|
||||
amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev,
|
||||
u8 id);
|
||||
|
||||
struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev,
|
||||
uint8_t id);
|
||||
void amdgpu_atombios_i2c_init(struct amdgpu_device *adev);
|
||||
|
||||
bool amdgpu_atombios_has_dce_engine_info(struct amdgpu_device *adev);
|
||||
|
||||
bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev);
|
||||
|
||||
int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev);
|
||||
|
||||
int amdgpu_atombios_get_gfx_info(struct amdgpu_device *adev);
|
||||
|
||||
int amdgpu_atombios_get_vram_width(struct amdgpu_device *adev);
|
||||
|
||||
bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev,
|
||||
struct amdgpu_atom_ss *ss,
|
||||
int id, u32 clock);
|
||||
|
||||
int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev,
|
||||
u8 clock_type,
|
||||
u32 clock,
|
||||
bool strobe_mode,
|
||||
struct atom_clock_dividers *dividers);
|
||||
|
||||
int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev,
|
||||
u32 clock,
|
||||
bool strobe_mode,
|
||||
struct atom_mpll_param *mpll_param);
|
||||
|
||||
void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev,
|
||||
u32 eng_clock, u32 mem_clock);
|
||||
|
||||
int amdgpu_atombios_get_leakage_id_from_vbios(struct amdgpu_device *adev,
|
||||
u16 *leakage_id);
|
||||
|
||||
int amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(struct amdgpu_device *adev,
|
||||
u16 *vddc, u16 *vddci,
|
||||
u16 virtual_voltage_id,
|
||||
u16 vbios_voltage_id);
|
||||
|
||||
int amdgpu_atombios_get_voltage_evv(struct amdgpu_device *adev,
|
||||
u16 virtual_voltage_id,
|
||||
u16 *voltage);
|
||||
|
||||
bool amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev,
|
||||
u8 voltage_type, u8 voltage_mode);
|
||||
|
||||
int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev,
|
||||
u8 voltage_type, u8 voltage_mode,
|
||||
struct atom_voltage_table *voltage_table);
|
||||
|
||||
int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev,
|
||||
u8 module_index,
|
||||
struct atom_mc_reg_table *reg_table);
|
||||
|
||||
bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev);
|
||||
|
||||
void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock);
|
||||
void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev,
|
||||
bool hung);
|
||||
bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev);
|
||||
|
||||
void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
|
||||
int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type,
|
||||
u16 voltage_id, u16 *voltage);
|
||||
int amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(struct amdgpu_device *adev,
|
||||
u16 *voltage,
|
||||
u16 leakage_idx);
|
||||
void amdgpu_atombios_get_default_voltages(struct amdgpu_device *adev,
|
||||
u16 *vddc, u16 *vddci, u16 *mvdd);
|
||||
int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev,
|
||||
u8 clock_type,
|
||||
u32 clock,
|
||||
bool strobe_mode,
|
||||
struct atom_clock_dividers *dividers);
|
||||
int amdgpu_atombios_get_svi2_info(struct amdgpu_device *adev,
|
||||
u8 voltage_type,
|
||||
u8 *svd_gpio_id, u8 *svc_gpio_id);
|
||||
|
||||
int amdgpu_atombios_get_data_table(struct amdgpu_device *adev,
|
||||
uint32_t table,
|
||||
uint16_t *size,
|
||||
uint8_t *frev,
|
||||
uint8_t *crev,
|
||||
uint8_t **addr);
|
||||
|
||||
void amdgpu_atombios_fini(struct amdgpu_device *adev);
|
||||
int amdgpu_atombios_init(struct amdgpu_device *adev);
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,71 @@
|
||||
/*
|
||||
* Copyright 2016 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
#include <drm/drm_print.h>
|
||||
|
||||
#include "atomfirmware.h"
|
||||
#include "amdgpu_atomfirmware.h"
|
||||
#include "atom.h"
|
||||
#include "atombios.h"
|
||||
#include "soc15_hw_ip.h"
|
||||
#include "common.h"
|
||||
|
||||
bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amd_fake_dev *adev)
|
||||
{
|
||||
int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
|
||||
firmwareinfo);
|
||||
uint16_t data_offset;
|
||||
|
||||
if (amdgpu_atom_parse_data_header(adev->atom_context, index, NULL,
|
||||
NULL, NULL, &data_offset))
|
||||
{
|
||||
struct atom_firmware_info_v3_1 *firmware_info =
|
||||
(struct atom_firmware_info_v3_1 *)(adev->atom_context->bios +
|
||||
data_offset);
|
||||
|
||||
if (le32_to_cpu(firmware_info->firmware_capability) &
|
||||
ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION)
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
void amdgpu_atomfirmware_scratch_regs_init(struct amd_fake_dev *adev)
|
||||
{
|
||||
int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
|
||||
firmwareinfo);
|
||||
uint16_t data_offset;
|
||||
|
||||
if (amdgpu_atom_parse_data_header(adev->atom_context, index, NULL,
|
||||
NULL, NULL, &data_offset))
|
||||
{
|
||||
struct atom_firmware_info_v3_1 *firmware_info =
|
||||
(struct atom_firmware_info_v3_1 *)(adev->atom_context->bios +
|
||||
data_offset);
|
||||
|
||||
adev->bios_scratch_reg_offset =
|
||||
le32_to_cpu(firmware_info->bios_scratch_reg_startaddr);
|
||||
DRM_INFO(
|
||||
"atomfirmware: bios_scratch_reg_offset initialized to %x\n",
|
||||
adev->bios_scratch_reg_offset);
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,33 @@
|
||||
/*
|
||||
* Copyright 2014 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __AMDGPU_ATOMFIRMWARE_H__
|
||||
#define __AMDGPU_ATOMFIRMWARE_H__
|
||||
|
||||
#define get_index_into_master_table(master_table, table_name) (offsetof(struct master_table, table_name) / sizeof(uint16_t))
|
||||
|
||||
struct amd_fake_dev;
|
||||
bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amd_fake_dev *adev);
|
||||
void amdgpu_atomfirmware_scratch_regs_init(struct amd_fake_dev *adev);
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,169 @@
|
||||
/*
|
||||
* Copyright 2008 Advanced Micro Devices, Inc.
|
||||
* Copyright 2008 Red Hat Inc.
|
||||
* Copyright 2009 Jerome Glisse.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Dave Airlie
|
||||
* Alex Deucher
|
||||
* Jerome Glisse
|
||||
*/
|
||||
|
||||
#include "atom.h"
|
||||
#include "common.h"
|
||||
|
||||
#include <linux/pci.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/acpi.h>
|
||||
#include <linux/types.h>
|
||||
#include <drm/drm_print.h>
|
||||
/*
|
||||
* BIOS.
|
||||
*/
|
||||
|
||||
#define AMD_VBIOS_SIGNATURE " 761295520"
|
||||
#define AMD_VBIOS_SIGNATURE_OFFSET 0x30
|
||||
#define AMD_VBIOS_SIGNATURE_SIZE sizeof(AMD_VBIOS_SIGNATURE)
|
||||
#define AMD_VBIOS_SIGNATURE_END (AMD_VBIOS_SIGNATURE_OFFSET + AMD_VBIOS_SIGNATURE_SIZE)
|
||||
#define AMD_IS_VALID_VBIOS(p) ((p)[0] == 0x55 && (p)[1] == 0xAA)
|
||||
#define AMD_VBIOS_LENGTH(p) ((p)[2] << 9)
|
||||
|
||||
/* Check if current bios is an ATOM BIOS.
|
||||
* Return true if it is ATOM BIOS. Otherwise, return false.
|
||||
*/
|
||||
static bool check_atom_bios(uint8_t *bios, size_t size)
|
||||
{
|
||||
uint16_t tmp, bios_header_start;
|
||||
|
||||
if (!bios || size < 0x49)
|
||||
{
|
||||
DRM_INFO("vbios mem is null or mem size is wrong\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!AMD_IS_VALID_VBIOS(bios))
|
||||
{
|
||||
DRM_INFO("BIOS signature incorrect %x %x\n", bios[0], bios[1]);
|
||||
return false;
|
||||
}
|
||||
|
||||
bios_header_start = bios[0x48] | (bios[0x49] << 8);
|
||||
if (!bios_header_start)
|
||||
{
|
||||
DRM_INFO("Can't locate bios header\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
tmp = bios_header_start + 4;
|
||||
if (size < tmp)
|
||||
{
|
||||
DRM_INFO("BIOS header is broken\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!memcmp(bios + tmp, "ATOM", 4) ||
|
||||
!memcmp(bios + tmp, "MOTA", 4))
|
||||
{
|
||||
DRM_DEBUG("ATOMBIOS detected\n");
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
bool amdgpu_read_bios(struct amd_fake_dev *adev)
|
||||
{
|
||||
uint8_t __iomem *bios;
|
||||
size_t size;
|
||||
|
||||
adev->bios = NULL;
|
||||
/* XXX: some cards may return 0 for rom size? ddx has a workaround */
|
||||
bios = pci_map_rom(adev->pdev, &size);
|
||||
if (!bios)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
adev->bios = kzalloc(size, GFP_KERNEL);
|
||||
if (adev->bios == NULL)
|
||||
{
|
||||
pci_unmap_rom(adev->pdev, bios);
|
||||
return false;
|
||||
}
|
||||
adev->bios_size = size;
|
||||
memcpy_fromio(adev->bios, bios, size);
|
||||
pci_unmap_rom(adev->pdev, bios);
|
||||
|
||||
if (!check_atom_bios(adev->bios, size))
|
||||
{
|
||||
kfree(adev->bios);
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool amdgpu_read_platform_bios(struct amd_fake_dev *adev)
|
||||
{
|
||||
phys_addr_t rom = adev->pdev->rom;
|
||||
size_t romlen = adev->pdev->romlen;
|
||||
void __iomem *bios;
|
||||
|
||||
adev->bios = NULL;
|
||||
|
||||
if (!rom || romlen == 0)
|
||||
return false;
|
||||
|
||||
adev->bios = kzalloc(romlen, GFP_KERNEL);
|
||||
if (!adev->bios)
|
||||
return false;
|
||||
|
||||
bios = ioremap(rom, romlen);
|
||||
if (!bios)
|
||||
goto free_bios;
|
||||
|
||||
memcpy_fromio(adev->bios, bios, romlen);
|
||||
iounmap(bios);
|
||||
|
||||
if (!check_atom_bios(adev->bios, romlen))
|
||||
goto free_bios;
|
||||
|
||||
adev->bios_size = romlen;
|
||||
|
||||
return true;
|
||||
free_bios:
|
||||
kfree(adev->bios);
|
||||
return false;
|
||||
}
|
||||
|
||||
bool amdgpu_get_bios(struct amd_fake_dev *adev)
|
||||
{
|
||||
if (amdgpu_read_bios(adev))
|
||||
goto success;
|
||||
|
||||
if (amdgpu_read_platform_bios(adev))
|
||||
goto success;
|
||||
|
||||
DRM_ERROR("Unable to locate a BIOS ROM\n");
|
||||
return false;
|
||||
|
||||
success:
|
||||
return true;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,164 @@
|
||||
/*
|
||||
* Copyright 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Author: Stanislaw Skowronek
|
||||
*/
|
||||
|
||||
#ifndef ATOM_H
|
||||
#define ATOM_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/mutex.h>
|
||||
|
||||
struct drm_device;
|
||||
|
||||
#define ATOM_BIOS_MAGIC 0xAA55
|
||||
#define ATOM_ATI_MAGIC_PTR 0x30
|
||||
#define ATOM_ATI_MAGIC " 761295520"
|
||||
#define ATOM_ROM_TABLE_PTR 0x48
|
||||
#define ATOM_ROM_PART_NUMBER_PTR 0x6E
|
||||
|
||||
#define ATOM_ROM_MAGIC "ATOM"
|
||||
#define ATOM_ROM_MAGIC_PTR 4
|
||||
|
||||
#define ATOM_ROM_MSG_PTR 0x10
|
||||
#define ATOM_ROM_CMD_PTR 0x1E
|
||||
#define ATOM_ROM_DATA_PTR 0x20
|
||||
|
||||
#define ATOM_CMD_INIT 0
|
||||
#define ATOM_CMD_SETSCLK 0x0A
|
||||
#define ATOM_CMD_SETMCLK 0x0B
|
||||
#define ATOM_CMD_SETPCLK 0x0C
|
||||
#define ATOM_CMD_SPDFANCNTL 0x39
|
||||
|
||||
#define ATOM_DATA_FWI_PTR 0xC
|
||||
#define ATOM_DATA_IIO_PTR 0x32
|
||||
|
||||
#define ATOM_FWI_DEFSCLK_PTR 8
|
||||
#define ATOM_FWI_DEFMCLK_PTR 0xC
|
||||
#define ATOM_FWI_MAXSCLK_PTR 0x24
|
||||
#define ATOM_FWI_MAXMCLK_PTR 0x28
|
||||
|
||||
#define ATOM_CT_SIZE_PTR 0
|
||||
#define ATOM_CT_WS_PTR 4
|
||||
#define ATOM_CT_PS_PTR 5
|
||||
#define ATOM_CT_PS_MASK 0x7F
|
||||
#define ATOM_CT_CODE_PTR 6
|
||||
|
||||
#define ATOM_OP_CNT 127
|
||||
#define ATOM_OP_EOT 91
|
||||
|
||||
#define ATOM_CASE_MAGIC 0x63
|
||||
#define ATOM_CASE_END 0x5A5A
|
||||
|
||||
#define ATOM_ARG_REG 0
|
||||
#define ATOM_ARG_PS 1
|
||||
#define ATOM_ARG_WS 2
|
||||
#define ATOM_ARG_FB 3
|
||||
#define ATOM_ARG_ID 4
|
||||
#define ATOM_ARG_IMM 5
|
||||
#define ATOM_ARG_PLL 6
|
||||
#define ATOM_ARG_MC 7
|
||||
|
||||
#define ATOM_SRC_DWORD 0
|
||||
#define ATOM_SRC_WORD0 1
|
||||
#define ATOM_SRC_WORD8 2
|
||||
#define ATOM_SRC_WORD16 3
|
||||
#define ATOM_SRC_BYTE0 4
|
||||
#define ATOM_SRC_BYTE8 5
|
||||
#define ATOM_SRC_BYTE16 6
|
||||
#define ATOM_SRC_BYTE24 7
|
||||
|
||||
#define ATOM_WS_QUOTIENT 0x40
|
||||
#define ATOM_WS_REMAINDER 0x41
|
||||
#define ATOM_WS_DATAPTR 0x42
|
||||
#define ATOM_WS_SHIFT 0x43
|
||||
#define ATOM_WS_OR_MASK 0x44
|
||||
#define ATOM_WS_AND_MASK 0x45
|
||||
#define ATOM_WS_FB_WINDOW 0x46
|
||||
#define ATOM_WS_ATTRIBUTES 0x47
|
||||
#define ATOM_WS_REGPTR 0x48
|
||||
|
||||
#define ATOM_IIO_NOP 0
|
||||
#define ATOM_IIO_START 1
|
||||
#define ATOM_IIO_READ 2
|
||||
#define ATOM_IIO_WRITE 3
|
||||
#define ATOM_IIO_CLEAR 4
|
||||
#define ATOM_IIO_SET 5
|
||||
#define ATOM_IIO_MOVE_INDEX 6
|
||||
#define ATOM_IIO_MOVE_ATTR 7
|
||||
#define ATOM_IIO_MOVE_DATA 8
|
||||
#define ATOM_IIO_END 9
|
||||
|
||||
#define ATOM_IO_MM 0
|
||||
#define ATOM_IO_PCI 1
|
||||
#define ATOM_IO_SYSIO 2
|
||||
#define ATOM_IO_IIO 0x80
|
||||
|
||||
struct card_info
|
||||
{
|
||||
struct drm_device *dev;
|
||||
void (*reg_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */
|
||||
uint32_t (*reg_read)(struct card_info *, uint32_t); /* filled by driver */
|
||||
void (*ioreg_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */
|
||||
uint32_t (*ioreg_read)(struct card_info *, uint32_t); /* filled by driver */
|
||||
void (*mc_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */
|
||||
uint32_t (*mc_read)(struct card_info *, uint32_t); /* filled by driver */
|
||||
void (*pll_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */
|
||||
uint32_t (*pll_read)(struct card_info *, uint32_t); /* filled by driver */
|
||||
};
|
||||
|
||||
struct atom_context
|
||||
{
|
||||
struct card_info *card;
|
||||
struct mutex mutex;
|
||||
void *bios;
|
||||
uint32_t cmd_table, data_table;
|
||||
uint16_t *iio;
|
||||
|
||||
uint16_t data_block;
|
||||
uint32_t fb_base;
|
||||
uint32_t divmul[2];
|
||||
uint16_t io_attr;
|
||||
uint16_t reg_block;
|
||||
uint8_t shift;
|
||||
int cs_equal, cs_above;
|
||||
int io_mode;
|
||||
uint32_t *scratch;
|
||||
int scratch_size_bytes;
|
||||
char vbios_version[20];
|
||||
};
|
||||
|
||||
extern int amdgpu_atom_debug;
|
||||
|
||||
struct atom_context *amdgpu_atom_parse(struct card_info *, void *);
|
||||
int amdgpu_atom_execute_table(struct atom_context *, int, uint32_t *);
|
||||
int amdgpu_atom_asic_init(struct atom_context *);
|
||||
void amdgpu_atom_destroy(struct atom_context *);
|
||||
bool amdgpu_atom_parse_data_header(struct atom_context *ctx, int index, uint16_t *size,
|
||||
uint8_t *frev, uint8_t *crev, uint16_t *data_start);
|
||||
bool amdgpu_atom_parse_cmd_header(struct atom_context *ctx, int index,
|
||||
uint8_t *frev, uint8_t *crev);
|
||||
#include "atom-types.h"
|
||||
#include "atombios.h"
|
||||
#include "ObjectID.h"
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,48 @@
|
||||
/*
|
||||
* Copyright 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Author: Stanislaw Skowronek
|
||||
*/
|
||||
|
||||
#ifndef ATOM_BITS_H
|
||||
#define ATOM_BITS_H
|
||||
|
||||
static inline uint8_t get_u8(void *bios, int ptr)
|
||||
{
|
||||
return ((unsigned char *)bios)[ptr];
|
||||
}
|
||||
#define U8(ptr) get_u8(ctx->ctx->bios, (ptr))
|
||||
#define CU8(ptr) get_u8(ctx->bios, (ptr))
|
||||
static inline uint16_t get_u16(void *bios, int ptr)
|
||||
{
|
||||
return get_u8(bios ,ptr)|(((uint16_t)get_u8(bios, ptr+1))<<8);
|
||||
}
|
||||
#define U16(ptr) get_u16(ctx->ctx->bios, (ptr))
|
||||
#define CU16(ptr) get_u16(ctx->bios, (ptr))
|
||||
static inline uint32_t get_u32(void *bios, int ptr)
|
||||
{
|
||||
return get_u16(bios, ptr)|(((uint32_t)get_u16(bios, ptr+2))<<16);
|
||||
}
|
||||
#define U32(ptr) get_u32(ctx->ctx->bios, (ptr))
|
||||
#define CU32(ptr) get_u32(ctx->bios, (ptr))
|
||||
#define CSTR(ptr) (((char *)(ctx->bios))+(ptr))
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,100 @@
|
||||
/*
|
||||
* Copyright 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Author: Stanislaw Skowronek
|
||||
*/
|
||||
|
||||
#ifndef ATOM_NAMES_H
|
||||
#define ATOM_NAMES_H
|
||||
|
||||
#include "atom.h"
|
||||
|
||||
#ifdef ATOM_DEBUG
|
||||
|
||||
#define ATOM_OP_NAMES_CNT 123
|
||||
static char *atom_op_names[ATOM_OP_NAMES_CNT] = {
|
||||
"RESERVED", "MOVE_REG", "MOVE_PS", "MOVE_WS", "MOVE_FB", "MOVE_PLL",
|
||||
"MOVE_MC", "AND_REG", "AND_PS", "AND_WS", "AND_FB", "AND_PLL", "AND_MC",
|
||||
"OR_REG", "OR_PS", "OR_WS", "OR_FB", "OR_PLL", "OR_MC", "SHIFT_LEFT_REG",
|
||||
"SHIFT_LEFT_PS", "SHIFT_LEFT_WS", "SHIFT_LEFT_FB", "SHIFT_LEFT_PLL",
|
||||
"SHIFT_LEFT_MC", "SHIFT_RIGHT_REG", "SHIFT_RIGHT_PS", "SHIFT_RIGHT_WS",
|
||||
"SHIFT_RIGHT_FB", "SHIFT_RIGHT_PLL", "SHIFT_RIGHT_MC", "MUL_REG",
|
||||
"MUL_PS", "MUL_WS", "MUL_FB", "MUL_PLL", "MUL_MC", "DIV_REG", "DIV_PS",
|
||||
"DIV_WS", "DIV_FB", "DIV_PLL", "DIV_MC", "ADD_REG", "ADD_PS", "ADD_WS",
|
||||
"ADD_FB", "ADD_PLL", "ADD_MC", "SUB_REG", "SUB_PS", "SUB_WS", "SUB_FB",
|
||||
"SUB_PLL", "SUB_MC", "SET_ATI_PORT", "SET_PCI_PORT", "SET_SYS_IO_PORT",
|
||||
"SET_REG_BLOCK", "SET_FB_BASE", "COMPARE_REG", "COMPARE_PS",
|
||||
"COMPARE_WS", "COMPARE_FB", "COMPARE_PLL", "COMPARE_MC", "SWITCH",
|
||||
"JUMP", "JUMP_EQUAL", "JUMP_BELOW", "JUMP_ABOVE", "JUMP_BELOW_OR_EQUAL",
|
||||
"JUMP_ABOVE_OR_EQUAL", "JUMP_NOT_EQUAL", "TEST_REG", "TEST_PS", "TEST_WS",
|
||||
"TEST_FB", "TEST_PLL", "TEST_MC", "DELAY_MILLISEC", "DELAY_MICROSEC",
|
||||
"CALL_TABLE", "REPEAT", "CLEAR_REG", "CLEAR_PS", "CLEAR_WS", "CLEAR_FB",
|
||||
"CLEAR_PLL", "CLEAR_MC", "NOP", "EOT", "MASK_REG", "MASK_PS", "MASK_WS",
|
||||
"MASK_FB", "MASK_PLL", "MASK_MC", "POST_CARD", "BEEP", "SAVE_REG",
|
||||
"RESTORE_REG", "SET_DATA_BLOCK", "XOR_REG", "XOR_PS", "XOR_WS", "XOR_FB",
|
||||
"XOR_PLL", "XOR_MC", "SHL_REG", "SHL_PS", "SHL_WS", "SHL_FB", "SHL_PLL",
|
||||
"SHL_MC", "SHR_REG", "SHR_PS", "SHR_WS", "SHR_FB", "SHR_PLL", "SHR_MC",
|
||||
"DEBUG", "CTB_DS",
|
||||
};
|
||||
|
||||
#define ATOM_TABLE_NAMES_CNT 74
|
||||
static char *atom_table_names[ATOM_TABLE_NAMES_CNT] = {
|
||||
"ASIC_Init", "GetDisplaySurfaceSize", "ASIC_RegistersInit",
|
||||
"VRAM_BlockVenderDetection", "SetClocksRatio", "MemoryControllerInit",
|
||||
"GPIO_PinInit", "MemoryParamAdjust", "DVOEncoderControl",
|
||||
"GPIOPinControl", "SetEngineClock", "SetMemoryClock", "SetPixelClock",
|
||||
"DynamicClockGating", "ResetMemoryDLL", "ResetMemoryDevice",
|
||||
"MemoryPLLInit", "EnableMemorySelfRefresh", "AdjustMemoryController",
|
||||
"EnableASIC_StaticPwrMgt", "ASIC_StaticPwrMgtStatusChange",
|
||||
"DAC_LoadDetection", "TMDS2EncoderControl", "LCD1OutputControl",
|
||||
"DAC1EncoderControl", "DAC2EncoderControl", "DVOOutputControl",
|
||||
"CV1OutputControl", "SetCRTC_DPM_State", "TVEncoderControl",
|
||||
"TMDS1EncoderControl", "LVDSEncoderControl", "TV1OutputControl",
|
||||
"EnableScaler", "BlankCRTC", "EnableCRTC", "GetPixelClock",
|
||||
"EnableVGA_Render", "EnableVGA_Access", "SetCRTC_Timing",
|
||||
"SetCRTC_OverScan", "SetCRTC_Replication", "SelectCRTC_Source",
|
||||
"EnableGraphSurfaces", "UpdateCRTC_DoubleBufferRegisters",
|
||||
"LUT_AutoFill", "EnableHW_IconCursor", "GetMemoryClock",
|
||||
"GetEngineClock", "SetCRTC_UsingDTDTiming", "TVBootUpStdPinDetection",
|
||||
"DFP2OutputControl", "VRAM_BlockDetectionByStrap", "MemoryCleanUp",
|
||||
"ReadEDIDFromHWAssistedI2C", "WriteOneByteToHWAssistedI2C",
|
||||
"ReadHWAssistedI2CStatus", "SpeedFanControl", "PowerConnectorDetection",
|
||||
"MC_Synchronization", "ComputeMemoryEnginePLL", "MemoryRefreshConversion",
|
||||
"VRAM_GetCurrentInfoBlock", "DynamicMemorySettings", "MemoryTraining",
|
||||
"EnableLVDS_SS", "DFP1OutputControl", "SetVoltage", "CRT1OutputControl",
|
||||
"CRT2OutputControl", "SetupHWAssistedI2CStatus", "ClockSource",
|
||||
"MemoryDeviceInit", "EnableYUV",
|
||||
};
|
||||
|
||||
#define ATOM_IO_NAMES_CNT 5
|
||||
static char *atom_io_names[ATOM_IO_NAMES_CNT] = {
|
||||
"MM", "PLL", "MC", "PCIE", "PCIE PORT",
|
||||
};
|
||||
|
||||
#else
|
||||
|
||||
#define ATOM_OP_NAMES_CNT 0
|
||||
#define ATOM_TABLE_NAMES_CNT 0
|
||||
#define ATOM_IO_NAMES_CNT 0
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,42 @@
|
||||
/*
|
||||
* Copyright 2008 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Author: Dave Airlie
|
||||
*/
|
||||
|
||||
#ifndef ATOM_TYPES_H
|
||||
#define ATOM_TYPES_H
|
||||
|
||||
/* sync atom types to kernel types */
|
||||
|
||||
typedef uint16_t USHORT;
|
||||
typedef uint32_t ULONG;
|
||||
typedef uint8_t UCHAR;
|
||||
|
||||
|
||||
#ifndef ATOM_BIG_ENDIAN
|
||||
#if defined(__BIG_ENDIAN)
|
||||
#define ATOM_BIG_ENDIAN 1
|
||||
#else
|
||||
#define ATOM_BIG_ENDIAN 0
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,86 @@
|
||||
/****************************************************************************\
|
||||
*
|
||||
* File Name atomfirmwareid.h
|
||||
*
|
||||
* Description ATOM BIOS command/data table ID definition header file
|
||||
*
|
||||
* Copyright 2016 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
|
||||
* and associated documentation files (the "Software"), to deal in the Software without restriction,
|
||||
* including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all copies or substantial
|
||||
* portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
\****************************************************************************/
|
||||
|
||||
#ifndef _ATOMFIRMWAREID_H_
|
||||
#define _ATOMFIRMWAREID_H_
|
||||
|
||||
enum atom_master_data_table_id
|
||||
{
|
||||
VBIOS_DATA_TBL_ID__UTILITY_PIPELINE,
|
||||
VBIOS_DATA_TBL_ID__MULTIMEDIA_INF,
|
||||
VBIOS_DATA_TBL_ID__FIRMWARE_INF,
|
||||
VBIOS_DATA_TBL_ID__LCD_INF,
|
||||
VBIOS_DATA_TBL_ID__SMU_INF,
|
||||
VBIOS_DATA_TBL_ID__VRAM_USAGE_BY_FIRMWARE,
|
||||
VBIOS_DATA_TBL_ID__GPIO_PIN_LUT,
|
||||
VBIOS_DATA_TBL_ID__GFX_INF,
|
||||
VBIOS_DATA_TBL_ID__POWER_PLAY_INF,
|
||||
VBIOS_DATA_TBL_ID__DISPLAY_OBJECT_INF,
|
||||
VBIOS_DATA_TBL_ID__INDIRECT_IO_ACCESS,
|
||||
VBIOS_DATA_TBL_ID__UMC_INF,
|
||||
VBIOS_DATA_TBL_ID__DCE_INF,
|
||||
VBIOS_DATA_TBL_ID__VRAM_INF,
|
||||
VBIOS_DATA_TBL_ID__INTEGRATED_SYS_INF,
|
||||
VBIOS_DATA_TBL_ID__ASIC_PROFILING_INF,
|
||||
VBIOS_DATA_TBL_ID__VOLTAGE_OBJ_INF,
|
||||
|
||||
VBIOS_DATA_TBL_ID__UNDEFINED,
|
||||
};
|
||||
|
||||
enum atom_master_command_table_id
|
||||
{
|
||||
VBIOS_CMD_TBL_ID__ASIC_INIT,
|
||||
VBIOS_CMD_TBL_ID__DIGX_ENCODER_CONTROL,
|
||||
VBIOS_CMD_TBL_ID__SET_ENGINE_CLOCK,
|
||||
VBIOS_CMD_TBL_ID__SET_MEMORY_CLOCK,
|
||||
VBIOS_CMD_TBL_ID__SET_PIXEL_CLOCK,
|
||||
VBIOS_CMD_TBL_ID__ENABLE_DISP_POWER_GATING,
|
||||
VBIOS_CMD_TBL_ID__BLANK_CRTC,
|
||||
VBIOS_CMD_TBL_ID__ENABLE_CRTC,
|
||||
VBIOS_CMD_TBL_ID__GET_SMU_CLOCK_INFO,
|
||||
VBIOS_CMD_TBL_ID__SELECT_CRTC_SOURCE,
|
||||
VBIOS_CMD_TBL_ID__SET_DCE_CLOCK,
|
||||
VBIOS_CMD_TBL_ID__GET_MEMORY_CLOCK,
|
||||
VBIOS_CMD_TBL_ID__GET_ENGINE_CLOCK,
|
||||
VBIOS_CMD_TBL_ID__SET_CRTC_USING_DTD_TIMING,
|
||||
VBIOS_CMD_TBL_ID__EXTENAL_ENCODER_CONTROL,
|
||||
VBIOS_CMD_TBL_ID__PROCESS_I2C_CHANNEL_TRANSACTION,
|
||||
VBIOS_CMD_TBL_ID__COMPUTE_GPU_CLOCK_PARAM,
|
||||
VBIOS_CMD_TBL_ID__DYNAMIC_MEMORY_SETTINGS,
|
||||
VBIOS_CMD_TBL_ID__MEMORY_TRAINING,
|
||||
VBIOS_CMD_TBL_ID__SET_VOLTAGE,
|
||||
VBIOS_CMD_TBL_ID__DIG1_TRANSMITTER_CONTROL,
|
||||
VBIOS_CMD_TBL_ID__PROCESS_AUX_CHANNEL_TRANSACTION,
|
||||
VBIOS_CMD_TBL_ID__GET_VOLTAGE_INF,
|
||||
|
||||
VBIOS_CMD_TBL_ID__UNDEFINED,
|
||||
};
|
||||
|
||||
|
||||
|
||||
#endif /* _ATOMFIRMWAREID_H_ */
|
||||
/* ### EOF ### */
|
||||
@ -0,0 +1,376 @@
|
||||
/*
|
||||
* Copyright 2017 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _PSP_TEE_GFX_IF_H_
|
||||
#define _PSP_TEE_GFX_IF_H_
|
||||
|
||||
#define PSP_GFX_CMD_BUF_VERSION 0x00000001
|
||||
|
||||
#define GFX_CMD_STATUS_MASK 0x0000FFFF
|
||||
#define GFX_CMD_ID_MASK 0x000F0000
|
||||
#define GFX_CMD_RESERVED_MASK 0x7FF00000
|
||||
#define GFX_CMD_RESPONSE_MASK 0x80000000
|
||||
|
||||
/* USBC PD FW version retrieval command */
|
||||
#define C2PMSG_CMD_GFX_USB_PD_FW_VER 0x2000000
|
||||
|
||||
/* TEE Gfx Command IDs for the register interface.
|
||||
* Command ID must be between 0x00010000 and 0x000F0000.
|
||||
*/
|
||||
enum psp_gfx_crtl_cmd_id
|
||||
{
|
||||
GFX_CTRL_CMD_ID_INIT_RBI_RING = 0x00010000, /* initialize RBI ring */
|
||||
GFX_CTRL_CMD_ID_INIT_GPCOM_RING = 0x00020000, /* initialize GPCOM ring */
|
||||
GFX_CTRL_CMD_ID_DESTROY_RINGS = 0x00030000, /* destroy rings */
|
||||
GFX_CTRL_CMD_ID_CAN_INIT_RINGS = 0x00040000, /* is it allowed to initialized the rings */
|
||||
GFX_CTRL_CMD_ID_ENABLE_INT = 0x00050000, /* enable PSP-to-Gfx interrupt */
|
||||
GFX_CTRL_CMD_ID_DISABLE_INT = 0x00060000, /* disable PSP-to-Gfx interrupt */
|
||||
GFX_CTRL_CMD_ID_MODE1_RST = 0x00070000, /* trigger the Mode 1 reset */
|
||||
GFX_CTRL_CMD_ID_GBR_IH_SET = 0x00080000, /* set Gbr IH_RB_CNTL registers */
|
||||
GFX_CTRL_CMD_ID_CONSUME_CMD = 0x000A0000, /* send interrupt to psp for updating write pointer of vf */
|
||||
GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING = 0x000C0000, /* destroy GPCOM ring */
|
||||
|
||||
GFX_CTRL_CMD_ID_MAX = 0x000F0000, /* max command ID */
|
||||
};
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
NOTE: All physical addresses used in this interface are actually
|
||||
GPU Virtual Addresses.
|
||||
*/
|
||||
|
||||
|
||||
/* Control registers of the TEE Gfx interface. These are located in
|
||||
* SRBM-to-PSP mailbox registers (total 8 registers).
|
||||
*/
|
||||
struct psp_gfx_ctrl
|
||||
{
|
||||
volatile uint32_t cmd_resp; /* +0 Command/Response register for Gfx commands */
|
||||
volatile uint32_t rbi_wptr; /* +4 Write pointer (index) of RBI ring */
|
||||
volatile uint32_t rbi_rptr; /* +8 Read pointer (index) of RBI ring */
|
||||
volatile uint32_t gpcom_wptr; /* +12 Write pointer (index) of GPCOM ring */
|
||||
volatile uint32_t gpcom_rptr; /* +16 Read pointer (index) of GPCOM ring */
|
||||
volatile uint32_t ring_addr_lo; /* +20 bits [31:0] of GPU Virtual of ring buffer (VMID=0)*/
|
||||
volatile uint32_t ring_addr_hi; /* +24 bits [63:32] of GPU Virtual of ring buffer (VMID=0) */
|
||||
volatile uint32_t ring_buf_size; /* +28 Ring buffer size (in bytes) */
|
||||
|
||||
};
|
||||
|
||||
|
||||
/* Response flag is set in the command when command is completed by PSP.
|
||||
* Used in the GFX_CTRL.CmdResp.
|
||||
* When PSP GFX I/F is initialized, the flag is set.
|
||||
*/
|
||||
#define GFX_FLAG_RESPONSE 0x80000000
|
||||
|
||||
/* Gbr IH registers ID */
|
||||
enum ih_reg_id {
|
||||
IH_RB = 0, // IH_RB_CNTL
|
||||
IH_RB_RNG1 = 1, // IH_RB_CNTL_RING1
|
||||
IH_RB_RNG2 = 2, // IH_RB_CNTL_RING2
|
||||
};
|
||||
|
||||
/* Command to setup Gibraltar IH register */
|
||||
struct psp_gfx_cmd_gbr_ih_reg {
|
||||
uint32_t reg_value; /* Value to be set to the IH_RB_CNTL... register*/
|
||||
enum ih_reg_id reg_id; /* ID of the register */
|
||||
};
|
||||
|
||||
/* TEE Gfx Command IDs for the ring buffer interface. */
|
||||
enum psp_gfx_cmd_id
|
||||
{
|
||||
GFX_CMD_ID_LOAD_TA = 0x00000001, /* load TA */
|
||||
GFX_CMD_ID_UNLOAD_TA = 0x00000002, /* unload TA */
|
||||
GFX_CMD_ID_INVOKE_CMD = 0x00000003, /* send command to TA */
|
||||
GFX_CMD_ID_LOAD_ASD = 0x00000004, /* load ASD Driver */
|
||||
GFX_CMD_ID_SETUP_TMR = 0x00000005, /* setup TMR region */
|
||||
GFX_CMD_ID_LOAD_IP_FW = 0x00000006, /* load HW IP FW */
|
||||
GFX_CMD_ID_DESTROY_TMR = 0x00000007, /* destroy TMR region */
|
||||
GFX_CMD_ID_SAVE_RESTORE = 0x00000008, /* save/restore HW IP FW */
|
||||
GFX_CMD_ID_SETUP_VMR = 0x00000009, /* setup VMR region */
|
||||
GFX_CMD_ID_DESTROY_VMR = 0x0000000A, /* destroy VMR region */
|
||||
GFX_CMD_ID_PROG_REG = 0x0000000B, /* program regs */
|
||||
GFX_CMD_ID_CLEAR_VF_FW = 0x0000000D, /* Clear VF FW, to be used on VF shutdown. */
|
||||
/* IDs upto 0x1F are reserved for older programs (Raven, Vega 10/12/20) */
|
||||
GFX_CMD_ID_LOAD_TOC = 0x00000020, /* Load TOC and obtain TMR size */
|
||||
GFX_CMD_ID_AUTOLOAD_RLC = 0x00000021, /* Indicates all graphics fw loaded, start RLC autoload */
|
||||
};
|
||||
|
||||
/* Command to load Trusted Application binary into PSP OS. */
|
||||
struct psp_gfx_cmd_load_ta
|
||||
{
|
||||
uint32_t app_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of the TA binary (must be 4 KB aligned) */
|
||||
uint32_t app_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of the TA binary */
|
||||
uint32_t app_len; /* length of the TA binary in bytes */
|
||||
uint32_t cmd_buf_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of CMD buffer (must be 4 KB aligned) */
|
||||
uint32_t cmd_buf_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of CMD buffer */
|
||||
uint32_t cmd_buf_len; /* length of the CMD buffer in bytes; must be multiple of 4 KB */
|
||||
|
||||
/* Note: CmdBufLen can be set to 0. In this case no persistent CMD buffer is provided
|
||||
* for the TA. Each InvokeCommand can have dinamically mapped CMD buffer instead
|
||||
* of using global persistent buffer.
|
||||
*/
|
||||
};
|
||||
|
||||
|
||||
/* Command to Unload Trusted Application binary from PSP OS. */
|
||||
struct psp_gfx_cmd_unload_ta
|
||||
{
|
||||
uint32_t session_id; /* Session ID of the loaded TA to be unloaded */
|
||||
|
||||
};
|
||||
|
||||
|
||||
/* Shared buffers for InvokeCommand.
|
||||
*/
|
||||
struct psp_gfx_buf_desc
|
||||
{
|
||||
uint32_t buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of the buffer (must be 4 KB aligned) */
|
||||
uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of the buffer */
|
||||
uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB and no bigger than 64 MB) */
|
||||
|
||||
};
|
||||
|
||||
/* Max number of descriptors for one shared buffer (in how many different
|
||||
* physical locations one shared buffer can be stored). If buffer is too much
|
||||
* fragmented, error will be returned.
|
||||
*/
|
||||
#define GFX_BUF_MAX_DESC 64
|
||||
|
||||
struct psp_gfx_buf_list
|
||||
{
|
||||
uint32_t num_desc; /* number of buffer descriptors in the list */
|
||||
uint32_t total_size; /* total size of all buffers in the list in bytes (must be multiple of 4 KB) */
|
||||
struct psp_gfx_buf_desc buf_desc[GFX_BUF_MAX_DESC]; /* list of buffer descriptors */
|
||||
|
||||
/* total 776 bytes */
|
||||
};
|
||||
|
||||
/* Command to execute InvokeCommand entry point of the TA. */
|
||||
struct psp_gfx_cmd_invoke_cmd
|
||||
{
|
||||
uint32_t session_id; /* Session ID of the TA to be executed */
|
||||
uint32_t ta_cmd_id; /* Command ID to be sent to TA */
|
||||
struct psp_gfx_buf_list buf; /* one indirect buffer (scatter/gather list) */
|
||||
|
||||
};
|
||||
|
||||
|
||||
/* Command to setup TMR region. */
|
||||
struct psp_gfx_cmd_setup_tmr
|
||||
{
|
||||
uint32_t buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of TMR buffer (must be 4 KB aligned) */
|
||||
uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of TMR buffer */
|
||||
uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB) */
|
||||
|
||||
};
|
||||
|
||||
|
||||
/* FW types for GFX_CMD_ID_LOAD_IP_FW command. Limit 31. */
|
||||
enum psp_gfx_fw_type {
|
||||
GFX_FW_TYPE_NONE = 0, /* */
|
||||
GFX_FW_TYPE_CP_ME = 1, /* CP-ME VG + RV */
|
||||
GFX_FW_TYPE_CP_PFP = 2, /* CP-PFP VG + RV */
|
||||
GFX_FW_TYPE_CP_CE = 3, /* CP-CE VG + RV */
|
||||
GFX_FW_TYPE_CP_MEC = 4, /* CP-MEC FW VG + RV */
|
||||
GFX_FW_TYPE_CP_MEC_ME1 = 5, /* CP-MEC Jump Table 1 VG + RV */
|
||||
GFX_FW_TYPE_CP_MEC_ME2 = 6, /* CP-MEC Jump Table 2 VG */
|
||||
GFX_FW_TYPE_RLC_V = 7, /* RLC-V VG */
|
||||
GFX_FW_TYPE_RLC_G = 8, /* RLC-G VG + RV */
|
||||
GFX_FW_TYPE_SDMA0 = 9, /* SDMA0 VG + RV */
|
||||
GFX_FW_TYPE_SDMA1 = 10, /* SDMA1 VG */
|
||||
GFX_FW_TYPE_DMCU_ERAM = 11, /* DMCU-ERAM VG + RV */
|
||||
GFX_FW_TYPE_DMCU_ISR = 12, /* DMCU-ISR VG + RV */
|
||||
GFX_FW_TYPE_VCN = 13, /* VCN RV */
|
||||
GFX_FW_TYPE_UVD = 14, /* UVD VG */
|
||||
GFX_FW_TYPE_VCE = 15, /* VCE VG */
|
||||
GFX_FW_TYPE_ISP = 16, /* ISP RV */
|
||||
GFX_FW_TYPE_ACP = 17, /* ACP RV */
|
||||
GFX_FW_TYPE_SMU = 18, /* SMU VG */
|
||||
GFX_FW_TYPE_MMSCH = 19, /* MMSCH VG */
|
||||
GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM = 20, /* RLC GPM VG + RV */
|
||||
GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM = 21, /* RLC SRM VG + RV */
|
||||
GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL = 22, /* RLC CNTL VG + RV */
|
||||
GFX_FW_TYPE_UVD1 = 23, /* UVD1 VG-20 */
|
||||
GFX_FW_TYPE_TOC = 24, /* TOC NV-10 */
|
||||
GFX_FW_TYPE_RLC_P = 25, /* RLC P NV */
|
||||
GFX_FW_TYPE_RLX6 = 26, /* RLX6 NV */
|
||||
GFX_FW_TYPE_GLOBAL_TAP_DELAYS = 27, /* GLOBAL TAP DELAYS NV */
|
||||
GFX_FW_TYPE_SE0_TAP_DELAYS = 28, /* SE0 TAP DELAYS NV */
|
||||
GFX_FW_TYPE_SE1_TAP_DELAYS = 29, /* SE1 TAP DELAYS NV */
|
||||
GFX_FW_TYPE_GLOBAL_SE0_SE1_SKEW_DELAYS = 30, /* GLOBAL SE0/1 SKEW DELAYS NV */
|
||||
GFX_FW_TYPE_SDMA0_JT = 31, /* SDMA0 JT NV */
|
||||
GFX_FW_TYPE_SDMA1_JT = 32, /* SDNA1 JT NV */
|
||||
GFX_FW_TYPE_CP_MES = 33, /* CP MES NV */
|
||||
GFX_FW_TYPE_MES_STACK = 34, /* MES STACK NV */
|
||||
GFX_FW_TYPE_RLC_SRM_DRAM_SR = 35, /* RLC SRM DRAM NV */
|
||||
GFX_FW_TYPE_RLCG_SCRATCH_SR = 36, /* RLCG SCRATCH NV */
|
||||
GFX_FW_TYPE_RLCP_SCRATCH_SR = 37, /* RLCP SCRATCH NV */
|
||||
GFX_FW_TYPE_RLCV_SCRATCH_SR = 38, /* RLCV SCRATCH NV */
|
||||
GFX_FW_TYPE_RLX6_DRAM_SR = 39, /* RLX6 DRAM NV */
|
||||
GFX_FW_TYPE_SDMA0_PG_CONTEXT = 40, /* SDMA0 PG CONTEXT NV */
|
||||
GFX_FW_TYPE_SDMA1_PG_CONTEXT = 41, /* SDMA1 PG CONTEXT NV */
|
||||
GFX_FW_TYPE_GLOBAL_MUX_SELECT_RAM = 42, /* GLOBAL MUX SEL RAM NV */
|
||||
GFX_FW_TYPE_SE0_MUX_SELECT_RAM = 43, /* SE0 MUX SEL RAM NV */
|
||||
GFX_FW_TYPE_SE1_MUX_SELECT_RAM = 44, /* SE1 MUX SEL RAM NV */
|
||||
GFX_FW_TYPE_ACCUM_CTRL_RAM = 45, /* ACCUM CTRL RAM NV */
|
||||
GFX_FW_TYPE_RLCP_CAM = 46, /* RLCP CAM NV */
|
||||
GFX_FW_TYPE_RLC_SPP_CAM_EXT = 47, /* RLC SPP CAM EXT NV */
|
||||
GFX_FW_TYPE_RLX6_DRAM_BOOT = 48, /* RLX6 DRAM BOOT NV */
|
||||
GFX_FW_TYPE_VCN0_RAM = 49, /* VCN_RAM NV + RN */
|
||||
GFX_FW_TYPE_VCN1_RAM = 50, /* VCN_RAM NV + RN */
|
||||
GFX_FW_TYPE_DMUB = 51, /* DMUB RN */
|
||||
GFX_FW_TYPE_SDMA2 = 52, /* SDMA2 MI */
|
||||
GFX_FW_TYPE_SDMA3 = 53, /* SDMA3 MI */
|
||||
GFX_FW_TYPE_SDMA4 = 54, /* SDMA4 MI */
|
||||
GFX_FW_TYPE_SDMA5 = 55, /* SDMA5 MI */
|
||||
GFX_FW_TYPE_SDMA6 = 56, /* SDMA6 MI */
|
||||
GFX_FW_TYPE_SDMA7 = 57, /* SDMA7 MI */
|
||||
GFX_FW_TYPE_VCN1 = 58, /* VCN1 MI */
|
||||
GFX_FW_TYPE_MAX
|
||||
};
|
||||
|
||||
/* Command to load HW IP FW. */
|
||||
struct psp_gfx_cmd_load_ip_fw
|
||||
{
|
||||
uint32_t fw_phy_addr_lo; /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */
|
||||
uint32_t fw_phy_addr_hi; /* bits [63:32] of GPU Virtual address of FW location */
|
||||
uint32_t fw_size; /* FW buffer size in bytes */
|
||||
enum psp_gfx_fw_type fw_type; /* FW type */
|
||||
|
||||
};
|
||||
|
||||
/* Command to save/restore HW IP FW. */
|
||||
struct psp_gfx_cmd_save_restore_ip_fw
|
||||
{
|
||||
uint32_t save_fw; /* if set, command is used for saving fw otherwise for resetoring*/
|
||||
uint32_t save_restore_addr_lo; /* bits [31:0] of FB address of GART memory used as save/restore buffer (must be 4 KB aligned) */
|
||||
uint32_t save_restore_addr_hi; /* bits [63:32] of FB address of GART memory used as save/restore buffer */
|
||||
uint32_t buf_size; /* Size of the save/restore buffer in bytes */
|
||||
enum psp_gfx_fw_type fw_type; /* FW type */
|
||||
};
|
||||
|
||||
/* Command to setup register program */
|
||||
struct psp_gfx_cmd_reg_prog {
|
||||
uint32_t reg_value;
|
||||
uint32_t reg_id;
|
||||
};
|
||||
|
||||
/* Command to load TOC */
|
||||
struct psp_gfx_cmd_load_toc
|
||||
{
|
||||
uint32_t toc_phy_addr_lo; /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */
|
||||
uint32_t toc_phy_addr_hi; /* bits [63:32] of GPU Virtual address of FW location */
|
||||
uint32_t toc_size; /* FW buffer size in bytes */
|
||||
};
|
||||
|
||||
/* All GFX ring buffer commands. */
|
||||
union psp_gfx_commands
|
||||
{
|
||||
struct psp_gfx_cmd_load_ta cmd_load_ta;
|
||||
struct psp_gfx_cmd_unload_ta cmd_unload_ta;
|
||||
struct psp_gfx_cmd_invoke_cmd cmd_invoke_cmd;
|
||||
struct psp_gfx_cmd_setup_tmr cmd_setup_tmr;
|
||||
struct psp_gfx_cmd_load_ip_fw cmd_load_ip_fw;
|
||||
struct psp_gfx_cmd_save_restore_ip_fw cmd_save_restore_ip_fw;
|
||||
struct psp_gfx_cmd_reg_prog cmd_setup_reg_prog;
|
||||
struct psp_gfx_cmd_setup_tmr cmd_setup_vmr;
|
||||
struct psp_gfx_cmd_load_toc cmd_load_toc;
|
||||
};
|
||||
|
||||
/* Structure of GFX Response buffer.
|
||||
* For GPCOM I/F it is part of GFX_CMD_RESP buffer, for RBI
|
||||
* it is separate buffer.
|
||||
*/
|
||||
struct psp_gfx_resp
|
||||
{
|
||||
uint32_t status; /* +0 status of command execution */
|
||||
uint32_t session_id; /* +4 session ID in response to LoadTa command */
|
||||
uint32_t fw_addr_lo; /* +8 bits [31:0] of FW address within TMR (in response to cmd_load_ip_fw command) */
|
||||
uint32_t fw_addr_hi; /* +12 bits [63:32] of FW address within TMR (in response to cmd_load_ip_fw command) */
|
||||
uint32_t tmr_size; /* +16 size of the TMR to be reserved including MM fw and Gfx fw in response to cmd_load_toc command */
|
||||
|
||||
uint32_t reserved[3];
|
||||
|
||||
/* total 32 bytes */
|
||||
};
|
||||
|
||||
/* Structure of Command buffer pointed by psp_gfx_rb_frame.cmd_buf_addr_hi
|
||||
* and psp_gfx_rb_frame.cmd_buf_addr_lo.
|
||||
*/
|
||||
struct psp_gfx_cmd_resp
|
||||
{
|
||||
uint32_t buf_size; /* +0 total size of the buffer in bytes */
|
||||
uint32_t buf_version; /* +4 version of the buffer strusture; must be PSP_GFX_CMD_BUF_VERSION */
|
||||
uint32_t cmd_id; /* +8 command ID */
|
||||
|
||||
/* These fields are used for RBI only. They are all 0 in GPCOM commands
|
||||
*/
|
||||
uint32_t resp_buf_addr_lo; /* +12 bits [31:0] of GPU Virtual address of response buffer (must be 4 KB aligned) */
|
||||
uint32_t resp_buf_addr_hi; /* +16 bits [63:32] of GPU Virtual address of response buffer */
|
||||
uint32_t resp_offset; /* +20 offset within response buffer */
|
||||
uint32_t resp_buf_size; /* +24 total size of the response buffer in bytes */
|
||||
|
||||
union psp_gfx_commands cmd; /* +28 command specific structures */
|
||||
|
||||
uint8_t reserved_1[864 - sizeof(union psp_gfx_commands) - 28];
|
||||
|
||||
/* Note: Resp is part of this buffer for GPCOM ring. For RBI ring the response
|
||||
* is separate buffer pointed by resp_buf_addr_hi and resp_buf_addr_lo.
|
||||
*/
|
||||
struct psp_gfx_resp resp; /* +864 response */
|
||||
|
||||
uint8_t reserved_2[1024 - 864 - sizeof(struct psp_gfx_resp)];
|
||||
|
||||
/* total size 1024 bytes */
|
||||
};
|
||||
|
||||
|
||||
#define FRAME_TYPE_DESTROY 1 /* frame sent by KMD driver when UMD Scheduler context is destroyed*/
|
||||
|
||||
/* Structure of the Ring Buffer Frame */
|
||||
struct psp_gfx_rb_frame
|
||||
{
|
||||
uint32_t cmd_buf_addr_lo; /* +0 bits [31:0] of GPU Virtual address of command buffer (must be 4 KB aligned) */
|
||||
uint32_t cmd_buf_addr_hi; /* +4 bits [63:32] of GPU Virtual address of command buffer */
|
||||
uint32_t cmd_buf_size; /* +8 command buffer size in bytes */
|
||||
uint32_t fence_addr_lo; /* +12 bits [31:0] of GPU Virtual address of Fence for this frame */
|
||||
uint32_t fence_addr_hi; /* +16 bits [63:32] of GPU Virtual address of Fence for this frame */
|
||||
uint32_t fence_value; /* +20 Fence value */
|
||||
uint32_t sid_lo; /* +24 bits [31:0] of SID value (used only for RBI frames) */
|
||||
uint32_t sid_hi; /* +28 bits [63:32] of SID value (used only for RBI frames) */
|
||||
uint8_t vmid; /* +32 VMID value used for mapping of all addresses for this frame */
|
||||
uint8_t frame_type; /* +33 1: destory context frame, 0: all other frames; used only for RBI frames */
|
||||
uint8_t reserved1[2]; /* +34 reserved, must be 0 */
|
||||
uint32_t reserved2[7]; /* +36 reserved, must be 0 */
|
||||
/* total 64 bytes */
|
||||
};
|
||||
|
||||
#define PSP_ERR_UNKNOWN_COMMAND 0x00000100
|
||||
|
||||
enum tee_error_code {
|
||||
TEE_SUCCESS = 0x00000000,
|
||||
TEE_ERROR_NOT_SUPPORTED = 0xFFFF000A,
|
||||
};
|
||||
|
||||
#endif /* _PSP_TEE_GFX_IF_H_ */
|
||||
@ -0,0 +1,47 @@
|
||||
/*
|
||||
Vendor Reset - Vendor Specific Reset
|
||||
Copyright (C) 2020 Geoffrey McRae <geoff@hostfission.com>
|
||||
Copyright (C) 2020 Adam Madsen <adam@ajmadsen.com>
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License as published by the Free Software
|
||||
Foundation; either version 2 of the License, or (at your option) any later
|
||||
version.
|
||||
|
||||
This program is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
|
||||
PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along with
|
||||
this program; if not, write to the Free Software Foundation, Inc., 59 Temple
|
||||
Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include "amdgpu_discovery.h"
|
||||
|
||||
#include "common.h"
|
||||
#include "compat.h"
|
||||
#include "firmware.h"
|
||||
|
||||
int amd_fake_dev_init(struct amd_fake_dev *adev, struct vendor_reset_dev *vdev)
|
||||
{
|
||||
adev->pdev = vdev->pdev;
|
||||
adev->dev = &vdev->pdev->dev;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void amd_fake_dev_fini(struct amd_fake_dev *adev)
|
||||
{
|
||||
if (adev->mman.discovery_bin)
|
||||
amdgpu_discovery_fini(adev);
|
||||
|
||||
if (adev->atom_context)
|
||||
atom_bios_fini(adev);
|
||||
|
||||
if (adev->bios)
|
||||
{
|
||||
kfree(adev->bios);
|
||||
adev->bios = NULL;
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,89 @@
|
||||
/*
|
||||
Vendor Reset - Vendor Specific Reset
|
||||
Copyright (C) 2020 Geoffrey McRae <geoff@hostfission.com>
|
||||
Copyright (C) 2020 Adam Madsen <adam@ajmadsen.com>
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License as published by the Free Software
|
||||
Foundation; either version 2 of the License, or (at your option) any later
|
||||
version.
|
||||
|
||||
This program is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
|
||||
PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along with
|
||||
this program; if not, write to the Free Software Foundation, Inc., 59 Temple
|
||||
Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __VENDOR_RESET_COMPAT_H__
|
||||
#define __VENDOR_RESET_COMPAT_H__
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
/* from amdgpu.h */
|
||||
enum amd_hw_ip_block_type
|
||||
{
|
||||
GC_HWIP = 1,
|
||||
HDP_HWIP,
|
||||
SDMA0_HWIP,
|
||||
SDMA1_HWIP,
|
||||
SDMA2_HWIP,
|
||||
SDMA3_HWIP,
|
||||
SDMA4_HWIP,
|
||||
SDMA5_HWIP,
|
||||
SDMA6_HWIP,
|
||||
SDMA7_HWIP,
|
||||
MMHUB_HWIP,
|
||||
ATHUB_HWIP,
|
||||
NBIO_HWIP,
|
||||
MP0_HWIP,
|
||||
MP1_HWIP,
|
||||
UVD_HWIP,
|
||||
VCN_HWIP = UVD_HWIP,
|
||||
JPEG_HWIP = VCN_HWIP,
|
||||
VCE_HWIP,
|
||||
DF_HWIP,
|
||||
DCE_HWIP,
|
||||
OSSSYS_HWIP,
|
||||
SMUIO_HWIP,
|
||||
PWR_HWIP,
|
||||
NBIF_HWIP,
|
||||
THM_HWIP,
|
||||
CLK_HWIP,
|
||||
UMC_HWIP,
|
||||
RSMU_HWIP,
|
||||
MAX_HWIP
|
||||
};
|
||||
|
||||
#define HWIP_MAX_INSTANCE 8
|
||||
/* end from amdgpu.h */
|
||||
|
||||
#include "amdgpu_gfx.h"
|
||||
#include "amdgpu_ttm.h"
|
||||
#include "atom.h"
|
||||
|
||||
struct amd_fake_dev
|
||||
{
|
||||
uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
|
||||
struct amdgpu_gfx gfx;
|
||||
struct amdgpu_mman mman;
|
||||
|
||||
uint32_t bios_scratch_reg_offset;
|
||||
|
||||
uint32_t bios_size;
|
||||
uint8_t *bios;
|
||||
|
||||
struct card_info card_info;
|
||||
struct atom_context *atom_context;
|
||||
|
||||
struct pci_dev *pdev;
|
||||
struct device *dev;
|
||||
};
|
||||
|
||||
struct vendor_reset_dev;
|
||||
int amd_fake_dev_init(struct amd_fake_dev *adev, struct vendor_reset_dev *vdev);
|
||||
void amd_fake_dev_fini(struct amd_fake_dev *adev);
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,85 @@
|
||||
/*
|
||||
Vendor Reset - Vendor Specific Reset
|
||||
Copyright (C) 2020 Geoffrey McRae <geoff@hostfission.com>
|
||||
Copyright (C) 2020 Adam Madsen <adam@ajmadsen.com>
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License as published by the Free Software
|
||||
Foundation; either version 2 of the License, or (at your option) any later
|
||||
version.
|
||||
|
||||
This program is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
|
||||
PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along with
|
||||
this program; if not, write to the Free Software Foundation, Inc., 59 Temple
|
||||
Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include "atom.h"
|
||||
#include "amdgpu_atomfirmware.h"
|
||||
#include "compat.h"
|
||||
#include "common.h"
|
||||
#include "firmware.h"
|
||||
|
||||
#define to_adev(info) ((struct amd_fake_dev *)container_of(info, struct amd_fake_dev, card_info))
|
||||
|
||||
static uint32_t null_read(struct card_info *info, uint32_t reg)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void null_write(struct card_info *info, uint32_t reg, uint32_t val)
|
||||
{
|
||||
}
|
||||
|
||||
static void reg_write(struct card_info *info, uint32_t reg, uint32_t val)
|
||||
{
|
||||
struct amd_fake_dev *adev = to_adev(info);
|
||||
|
||||
WREG32(reg, val);
|
||||
}
|
||||
|
||||
static uint32_t reg_read(struct card_info *info, uint32_t reg)
|
||||
{
|
||||
struct amd_fake_dev *adev = to_adev(info);
|
||||
uint32_t r;
|
||||
|
||||
r = RREG32(reg);
|
||||
return r;
|
||||
}
|
||||
|
||||
int atom_bios_init(struct amd_fake_dev *adev)
|
||||
{
|
||||
struct card_info *info = &adev->card_info;
|
||||
|
||||
info->mc_read = info->pll_read = null_read;
|
||||
info->mc_write = info->pll_write = null_write;
|
||||
|
||||
info->reg_read = info->ioreg_read = reg_read;
|
||||
info->reg_write = info->ioreg_write = reg_write;
|
||||
|
||||
adev->atom_context = amdgpu_atom_parse(info, adev->bios);
|
||||
if (!adev->atom_context)
|
||||
{
|
||||
atom_bios_fini(adev);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
amdgpu_atomfirmware_scratch_regs_init(adev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void atom_bios_fini(struct amd_fake_dev *adev)
|
||||
{
|
||||
if (adev->atom_context)
|
||||
{
|
||||
kfree(adev->atom_context->scratch);
|
||||
kfree(adev->atom_context->iio);
|
||||
}
|
||||
kfree(adev->atom_context);
|
||||
adev->atom_context = NULL;
|
||||
}
|
||||
@ -0,0 +1,26 @@
|
||||
/*
|
||||
Vendor Reset - Vendor Specific Reset
|
||||
Copyright (C) 2020 Geoffrey McRae <geoff@hostfission.com>
|
||||
Copyright (C) 2020 Adam Madsen <adam@ajmadsen.com>
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License as published by the Free Software
|
||||
Foundation; either version 2 of the License, or (at your option) any later
|
||||
version.
|
||||
|
||||
This program is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
|
||||
PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along with
|
||||
this program; if not, write to the Free Software Foundation, Inc., 59 Temple
|
||||
Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __VENDOR_RESET_FIRMWARE_H__
|
||||
#define __VENDOR_RESET_FIRMWARE_H__
|
||||
|
||||
int atom_bios_init(struct amd_fake_dev *adev);
|
||||
void atom_bios_fini(struct amd_fake_dev *adev);
|
||||
|
||||
#endif
|
||||
@ -0,0 +1 @@
|
||||
vendor-reset
|
||||
Loading…
Reference in New Issue