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/*
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Vendor Reset - Vendor Specific Reset
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Copyright (C) 2020 Geoffrey McRae <geoff@hostfission.com>
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Copyright (C) 2020 Adam Madsen <adam@ajmadsen.com>
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This program is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free Software
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Foundation; either version 2 of the License, or (at your option) any later
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version.
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This program is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
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PARTICULAR PURPOSE. See the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __VENDOR_RESET_COMMON_H__
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#define __VENDOR_RESET_COMMON_H__
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#include <linux/kernel.h>
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#include "vendor-reset-dev.h"
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/* from amdgpu_discovery.c */
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#ifndef mmMM_INDEX
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#define mmRCC_CONFIG_MEMSIZE 0xde3
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#define mmMM_INDEX 0x0
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#define mmMM_INDEX_HI 0x6
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#define mmMM_DATA 0x1
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#define HW_ID_MAX 300
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#endif
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/* end from amdgpu_discovery.c */
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#define RREG32(reg) \
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({ \
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u32 __out; \
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if ((reg) < adev->private->mmio_size) \
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__out = readl(adev->private->mmio + (reg)); \
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else \
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{ \
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unsigned long __flags; \
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spin_lock_irqsave(&adev->private->reg_lock, __flags); \
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writel((reg), adev->private->mmio + mmMM_INDEX); \
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__out = readl(adev->private->mmio + mmMM_DATA); \
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spin_unlock_irqrestore(&adev->private->reg_lock, __flags); \
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} \
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__out; \
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})
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#define WREG32(reg, v) \
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do \
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{ \
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if ((reg) < adev->private->mmio_size) \
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writel(v, adev->private->mmio + (reg)); \
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else \
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{ \
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unsigned long __flags; \
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spin_lock_irqsave(&adev->private->reg_lock, __flags); \
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writel((reg), adev->private->mmio + mmMM_INDEX); \
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writel(v, adev->private->mmio + mmMM_DATA); \
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spin_unlock_irqrestore(&adev->private->reg_lock, __flags); \
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} \
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} while (0)
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#define WREG32_PCIE(reg, v) \
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do \
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{ \
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unsigned long __flags; \
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spin_lock_irqsave(&adev->private->pcie_lock, __flags); \
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WREG32(mmPCIE_INDEX2, reg); \
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(void)RREG32(mmPCIE_INDEX2); \
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WREG32(mmPCIE_DATA2, v); \
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(void)RREG32(mmPCIE_DATA2); \
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spin_unlock_irqrestore(&adev->private->pcie_lock, __flags); \
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} while (0)
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#define RREG32_PCIE(reg) \
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({ \
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unsigned long __flags; \
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u32 __tmp_read; \
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spin_lock_irqsave(&adev->private->pcie_lock, __flags); \
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WREG32(mmPCIE_INDEX2, reg); \
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(void)RREG32(mmPCIE_INDEX2); \
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__tmp_read = RREG32(mmPCIE_DATA2); \
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spin_unlock_irqrestore(&adev->private->pcie_lock, __flags); \
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__tmp_read; \
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})
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/* from smu_cm.c */
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/*
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* Although these are defined in each ASIC's specific header file.
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* They share the same definitions and values. That makes common
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* APIs for SMC messages issuing for all ASICs possible.
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*/
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#define mmMP1_SMN_C2PMSG_66 0x0282
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#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0
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#define mmMP1_SMN_C2PMSG_82 0x0292
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#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0
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#define mmMP1_SMN_C2PMSG_90 0x029a
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#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0
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#define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
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/* end from smu_cm.c */
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/* from amdgpu.h */
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enum amd_hw_ip_block_type
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{
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GC_HWIP = 1,
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HDP_HWIP,
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SDMA0_HWIP,
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SDMA1_HWIP,
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SDMA2_HWIP,
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SDMA3_HWIP,
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SDMA4_HWIP,
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SDMA5_HWIP,
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SDMA6_HWIP,
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SDMA7_HWIP,
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MMHUB_HWIP,
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ATHUB_HWIP,
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NBIO_HWIP,
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MP0_HWIP,
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MP1_HWIP,
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UVD_HWIP,
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VCN_HWIP = UVD_HWIP,
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JPEG_HWIP = VCN_HWIP,
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VCE_HWIP,
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DF_HWIP,
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DCE_HWIP,
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OSSSYS_HWIP,
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SMUIO_HWIP,
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PWR_HWIP,
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NBIF_HWIP,
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THM_HWIP,
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CLK_HWIP,
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UMC_HWIP,
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RSMU_HWIP,
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MAX_HWIP
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};
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#define HWIP_MAX_INSTANCE 8
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/* end from amdgpu.h */
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/* from hwmgr.h */
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enum BACO_STATE
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{
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BACO_STATE_OUT = 0,
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BACO_STATE_IN,
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};
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/* end from hwmgr.h */
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struct amd_fake_dev
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{
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uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
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struct device *dev;
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struct amd_vendor_private *private;
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};
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struct amd_vendor_private
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{
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u16 cfg;
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struct vendor_reset_dev *vdev;
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struct pci_saved_state *saved_state;
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struct amd_fake_dev adev;
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resource_size_t mmio_base;
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resource_size_t mmio_size;
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uint32_t __iomem *mmio;
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spinlock_t pcie_lock;
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spinlock_t reg_lock;
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struct mutex smu_lock;
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};
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#define amd_private(vdev) ((struct amd_vendor_private *)(vdev->vendor_private))
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int amd_common_pre_reset(struct vendor_reset_dev *);
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int amd_common_post_reset(struct vendor_reset_dev *);
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int smum_send_msg_to_smc(struct amd_fake_dev *adev, uint16_t msg, uint32_t *resp);
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#endif
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