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99 lines
3.8 KiB
Rust
99 lines
3.8 KiB
Rust
// SPDX-License-Identifier: MIT OR Apache-2.0
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//
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// Copyright (c) 2021-2022 Andre Richter <andre.o.richter@gmail.com>
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//! Translation table.
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#[cfg(target_arch = "aarch64")]
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#[path = "../../_arch/aarch64/memory/mmu/translation_table.rs"]
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mod arch_translation_table;
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use super::{AttributeFields, MemoryRegion};
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use crate::memory::{Address, Physical, Virtual};
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//--------------------------------------------------------------------------------------------------
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// Architectural Public Reexports
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//--------------------------------------------------------------------------------------------------
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#[cfg(target_arch = "aarch64")]
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pub use arch_translation_table::FixedSizeTranslationTable;
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//--------------------------------------------------------------------------------------------------
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// Public Definitions
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//--------------------------------------------------------------------------------------------------
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/// Translation table interfaces.
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pub mod interface {
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use super::*;
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/// Translation table operations.
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pub trait TranslationTable {
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/// Anything that needs to run before any of the other provided functions can be used.
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///
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/// # Safety
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///
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/// - Implementor must ensure that this function can run only once or is harmless if invoked
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/// multiple times.
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fn init(&mut self);
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/// The translation table's base address to be used for programming the MMU.
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fn phys_base_address(&self) -> Address<Physical>;
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/// Map the given virtual memory region to the given physical memory region.
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///
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/// # Safety
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///
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/// - Using wrong attributes can cause multiple issues of different nature in the system.
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/// - It is not required that the architectural implementation prevents aliasing. That is,
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/// mapping to the same physical memory using multiple virtual addresses, which would
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/// break Rust's ownership assumptions. This should be protected against in the kernel's
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/// generic MMU code.
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unsafe fn map_at(
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&mut self,
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virt_region: &MemoryRegion<Virtual>,
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phys_region: &MemoryRegion<Physical>,
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attr: &AttributeFields,
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) -> Result<(), &'static str>;
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}
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}
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//--------------------------------------------------------------------------------------------------
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// Testing
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//--------------------------------------------------------------------------------------------------
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#[cfg(test)]
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mod tests {
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use super::*;
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use crate::memory::mmu::{AccessPermissions, MemAttributes, PageAddress};
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use arch_translation_table::MinSizeTranslationTable;
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use interface::TranslationTable;
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use test_macros::kernel_test;
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/// Sanity checks for the TranslationTable implementation.
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#[kernel_test]
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fn translationtable_implementation_sanity() {
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// This will occupy a lot of space on the stack.
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let mut tables = MinSizeTranslationTable::new();
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tables.init();
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let virt_start_page_addr: PageAddress<Virtual> = PageAddress::from(0);
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let virt_end_exclusive_page_addr: PageAddress<Virtual> =
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virt_start_page_addr.checked_offset(5).unwrap();
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let phys_start_page_addr: PageAddress<Physical> = PageAddress::from(0);
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let phys_end_exclusive_page_addr: PageAddress<Physical> =
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phys_start_page_addr.checked_offset(5).unwrap();
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let virt_region = MemoryRegion::new(virt_start_page_addr, virt_end_exclusive_page_addr);
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let phys_region = MemoryRegion::new(phys_start_page_addr, phys_end_exclusive_page_addr);
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let attr = AttributeFields {
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mem_attributes: MemAttributes::CacheableDRAM,
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acc_perms: AccessPermissions::ReadWrite,
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execute_never: true,
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};
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unsafe { assert_eq!(tables.map_at(&virt_region, &phys_region, &attr), Ok(())) };
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}
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}
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