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184 lines
6.2 KiB
Rust
184 lines
6.2 KiB
Rust
// SPDX-License-Identifier: MIT OR Apache-2.0
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//
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// Copyright (c) 2018-2021 Andre Richter <andre.o.richter@gmail.com>
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//! Memory Management Unit Driver.
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//!
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//! Only 64 KiB granule is supported.
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//!
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//! # Orientation
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//!
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//! Since arch modules are imported into generic modules using the path attribute, the path of this
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//! file is:
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//!
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//! crate::memory::mmu::arch_mmu
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use crate::{
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bsp, memory,
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memory::{mmu::TranslationGranule, Address, Physical, Virtual},
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};
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use core::intrinsics::unlikely;
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use cortex_a::{asm::barrier, registers::*};
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use tock_registers::interfaces::{ReadWriteable, Readable, Writeable};
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//--------------------------------------------------------------------------------------------------
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// Private Definitions
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//--------------------------------------------------------------------------------------------------
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/// Memory Management Unit type.
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struct MemoryManagementUnit;
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//--------------------------------------------------------------------------------------------------
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// Public Definitions
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//--------------------------------------------------------------------------------------------------
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pub type Granule512MiB = TranslationGranule<{ 512 * 1024 * 1024 }>;
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pub type Granule64KiB = TranslationGranule<{ 64 * 1024 }>;
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/// Constants for indexing the MAIR_EL1.
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#[allow(dead_code)]
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pub mod mair {
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pub const DEVICE: u64 = 0;
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pub const NORMAL: u64 = 1;
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}
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//--------------------------------------------------------------------------------------------------
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// Global instances
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//--------------------------------------------------------------------------------------------------
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static MMU: MemoryManagementUnit = MemoryManagementUnit;
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//--------------------------------------------------------------------------------------------------
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// Private Code
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//--------------------------------------------------------------------------------------------------
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impl<const AS_SIZE: usize> memory::mmu::AddressSpace<AS_SIZE> {
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/// Checks for architectural restrictions.
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pub const fn arch_address_space_size_sanity_checks() {
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// Size must be at least one full 512 MiB table.
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assert!((AS_SIZE % Granule512MiB::SIZE) == 0);
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// Check for 48 bit virtual address size as maximum, which is supported by any ARMv8
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// version.
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assert!(AS_SIZE <= (1 << 48));
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}
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}
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impl MemoryManagementUnit {
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/// Setup function for the MAIR_EL1 register.
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fn set_up_mair(&self) {
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// Define the memory types being mapped.
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MAIR_EL1.write(
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// Attribute 1 - Cacheable normal DRAM.
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MAIR_EL1::Attr1_Normal_Outer::WriteBack_NonTransient_ReadWriteAlloc +
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MAIR_EL1::Attr1_Normal_Inner::WriteBack_NonTransient_ReadWriteAlloc +
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// Attribute 0 - Device.
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MAIR_EL1::Attr0_Device::nonGathering_nonReordering_EarlyWriteAck,
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);
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}
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/// Configure various settings of stage 1 of the EL1 translation regime.
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fn configure_translation_control(&self) {
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let t0sz = (64 - bsp::memory::mmu::KernelVirtAddrSpace::SIZE_SHIFT) as u64;
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TCR_EL1.write(
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TCR_EL1::TBI0::Used
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+ TCR_EL1::IPS::Bits_40
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+ TCR_EL1::TG0::KiB_64
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+ TCR_EL1::SH0::Inner
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+ TCR_EL1::ORGN0::WriteBack_ReadAlloc_WriteAlloc_Cacheable
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+ TCR_EL1::IRGN0::WriteBack_ReadAlloc_WriteAlloc_Cacheable
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+ TCR_EL1::EPD0::EnableTTBR0Walks
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+ TCR_EL1::A1::TTBR0
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+ TCR_EL1::T0SZ.val(t0sz)
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+ TCR_EL1::EPD1::DisableTTBR1Walks,
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);
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}
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}
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//--------------------------------------------------------------------------------------------------
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// Public Code
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//--------------------------------------------------------------------------------------------------
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/// Return a reference to the MMU instance.
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pub fn mmu() -> &'static impl memory::mmu::interface::MMU {
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&MMU
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}
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//------------------------------------------------------------------------------
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// OS Interface Code
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//------------------------------------------------------------------------------
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use memory::mmu::{MMUEnableError, TranslationError};
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impl memory::mmu::interface::MMU for MemoryManagementUnit {
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unsafe fn enable_mmu_and_caching(
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&self,
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phys_tables_base_addr: Address<Physical>,
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) -> Result<(), MMUEnableError> {
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if unlikely(self.is_enabled()) {
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return Err(MMUEnableError::AlreadyEnabled);
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}
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// Fail early if translation granule is not supported.
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if unlikely(!ID_AA64MMFR0_EL1.matches_all(ID_AA64MMFR0_EL1::TGran64::Supported)) {
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return Err(MMUEnableError::Other(
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"Translation granule not supported in HW",
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));
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}
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// Prepare the memory attribute indirection register.
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self.set_up_mair();
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// Set the "Translation Table Base Register".
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TTBR0_EL1.set_baddr(phys_tables_base_addr.into_usize() as u64);
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self.configure_translation_control();
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// Switch the MMU on.
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//
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// First, force all previous changes to be seen before the MMU is enabled.
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barrier::isb(barrier::SY);
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// Enable the MMU and turn on data and instruction caching.
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SCTLR_EL1.modify(SCTLR_EL1::M::Enable + SCTLR_EL1::C::Cacheable + SCTLR_EL1::I::Cacheable);
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// Force MMU init to complete before next instruction.
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barrier::isb(barrier::SY);
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Ok(())
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}
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#[inline(always)]
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fn is_enabled(&self) -> bool {
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SCTLR_EL1.matches_all(SCTLR_EL1::M::Enable)
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}
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fn try_virt_to_phys(
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&self,
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virt: Address<Virtual>,
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) -> Result<Address<Physical>, TranslationError> {
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if !self.is_enabled() {
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return Err(TranslationError::MMUDisabled);
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}
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let addr = virt.into_usize() as u64;
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unsafe {
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asm!(
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"AT S1E1R, {0}",
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in(reg) addr,
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options(readonly, nostack, preserves_flags)
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);
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}
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let par_el1 = PAR_EL1.extract();
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if par_el1.matches_all(PAR_EL1::F::TranslationAborted) {
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return Err(TranslationError::Aborted);
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}
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let phys_addr = (par_el1.read(PAR_EL1::PA) << 12) | (addr & 0xFFF);
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Ok(Address::new(phys_addr as usize))
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}
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}
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