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60 lines
2.2 KiB
Markdown
60 lines
2.2 KiB
Markdown
# Tutorial 0E - Cache Performance
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Now that we finally have virtual memory capabilities available, we also have
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fine grained control over `cacheability`. You've caught a glimpse already in the
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last tutorial, where we used page table entries to reference the `MAIR_EL1`
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register to indicate the cacheability of a page or block.
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Unfortunately, for the user it is often hard to grasp the advantage of caching
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in early stages of OS or bare-metal software development. This tutorial is a
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short interlude that tries to give you a feeling of what caching can do for
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performance.
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## Benchmark
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Let's write a tiny, arbitrary micro-benchmark to showcase the performance of
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operating with data on the same DRAM with caching enabled and disabled.
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### mmu.rs
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Therefore, we will map the same physical memory via two different virtual
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addresses. We set up our pagetables such that the virtual address `0x400000`
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points to the physical DRAM at `0x200000`, and we configure it as
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`non-cacheable` in the page tables.
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There is also an identity mapped block, which starts at virtual `0x200000` and
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points at physical `0x200000`. This time, the block is configured as cacheable.
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### benchmark.rs
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We write a little function that iteratively reads memory of five times the size
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of a `cacheline`, in steps of 8 bytes, aka one processor register at a time. We
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read the value, add 1, and write it back. This whole process is repeated
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`20_000` times.
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The benchmark function is called twice. Once for the cacheable and once for the
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non-cacheable virtual addresses. Remember that both virtual addresses point to
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the _same_ physical DRAM, so the difference in time that we will see will
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showcase how much faster it is to operate on DRAM with caching enabled.
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## Output
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On my Raspberry, I get the following results:
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```console
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ferris@box:~$ make raspboot
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[0] UART is live!
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[1] Press a key to continue booting... Greetings fellow Rustacean!
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[2] MMU online.
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Benchmarking non-cacheable DRAM modifications at virtual 0x0000000000400000, physical 0x0000000000200000:
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1040 miliseconds.
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Benchmarking cacheable DRAM modifications at virtual 0x0000000000200000, physical 0x0000000000200000:
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53 miliseconds.
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With caching, the function is 1800% faster!
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```
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Impressive, isn't it?
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