Commit Graph

18 Commits

Author SHA1 Message Date
Andre Richter
21e181c63a
Bump cortex-a to v1.1.0 2018-08-24 00:13:53 +02:00
Andre Richter
8175639399
Correct linker issues
The new target is not automatically using PIC.

Need some linker script corrections for errors that were hiding
previously, so that we don't accidentally generate alignment
exceptions on bss size variables that cause the target to fail.
2018-08-20 17:07:18 +02:00
Andre Richter
0d75a8eaf3
Use aarch64-unknown-none target in nightly 🎉
We have a generic target for writing bare-metal code
for 64-bit ARM architectures in upstream Rust now.

Use it to get rid of the fully custom target spec.

\o/
2018-08-19 23:42:24 +02:00
Andre Richter
0bd363f375
Sync with the newest Embedonomicon
https://github.com/rust-embedded/embedonomicon

Closes #3
2018-08-12 16:41:45 +02:00
Andre Richter
369dffa457
Make it compile on newest nightly 2018-07-16 21:37:40 +02:00
Andre Richter
747e902761
Rewrite for register-rs.
We now have the same API for MMIO and CPU registers.
Makes the code more concise, inntuitive, and improves readability.

https://crates.io/crates/register
2018-07-16 21:24:33 +02:00
Andre Richter
69d9890c4a
Update #[lang = "panic_fmt"] -> #[panic_implementation]
More info: https://users.rust-lang.org/t/psa-breaking-change-panic-fmt-language-item-removed-in-favor-of-panic-implementation/17875
2018-06-17 13:40:30 +02:00
Andre Richter
0ce1cde72c Add Deref trait in the spirit of cortex-m peripherals
Improves code readability; Reduces need for unsafe blocks on register
reads.

https://github.com/japaric/cortex-m/blob/master/src/peripheral/mod.rs
2018-04-13 22:05:50 +02:00
Andre Richter
32ef64b36e compiler_builtins are now mandatory; Add them.
In rust-lang/rust@679657b863 a breaking
change was introduced that now requires compiler_builtins. Add them,
and use the opportunity to kick out rlibc, since memset() et al. can
be provided by compiler intrinsics.
2018-04-08 13:28:57 +02:00
Andre Richter
036d6f0893 Change fence type, add more elaborate description 2018-04-07 12:18:04 +02:00
Andre Richter
d2636fc9ba Add compiler fence before mailbox signaling 2018-04-02 19:09:53 +02:00
Andre Richter
41d69fa594 Remove memory barrier again
Upon further reading, found out that RPi3 features an A53 CPU, which
is one of the ARMv8-A variants that in fact does _not_ have
out-of-order execution.
2018-04-02 19:09:49 +02:00
Andre Richter
de0e42142b stay closer to original 2018-04-02 17:44:05 +02:00
Andre Richter
989a9326ec Add memory barrier before mailbox calls 2018-04-01 21:45:26 +02:00
Andre Richter
b3c9e041e6 Add UART0 Hello World 2018-03-31 20:08:45 +02:00
bzt
a798ff59f4 Fixed issue #3 2018-01-13 21:34:05 +01:00
bzt
e1c97f2904 Fixed issue #2 2018-01-13 21:31:34 +01:00
bzt
7ace64ba9f Initial commit 2018-01-04 18:24:49 +01:00