From dea501712813ec561dec8cbabc376ea49e64a6df Mon Sep 17 00:00:00 2001 From: Andre Richter Date: Fri, 25 Oct 2019 09:26:37 +0200 Subject: [PATCH] move gpio funtion out of inner --- 05_safe_globals/README.md | 3 +- 06_drivers_gpio_uart/README.md | 54 ++++++++---------- 06_drivers_gpio_uart/kernel | Bin 83384 -> 83384 bytes 06_drivers_gpio_uart/kernel8.img | Bin 7920 -> 7920 bytes .../src/bsp/driver/bcm/bcm2xxx_gpio.rs | 43 +++++++------- 07_uart_chainloader/README.md | 3 +- 07_uart_chainloader/kernel | Bin 85224 -> 85224 bytes 07_uart_chainloader/kernel8.img | Bin 8824 -> 8824 bytes .../src/bsp/driver/bcm/bcm2xxx_gpio.rs | 43 +++++++------- 08_timestamps/README.md | 3 +- 08_timestamps/kernel | Bin 90936 -> 90936 bytes .../src/bsp/driver/bcm/bcm2xxx_gpio.rs | 43 +++++++------- 12 files changed, 91 insertions(+), 101 deletions(-) diff --git a/05_safe_globals/README.md b/05_safe_globals/README.md index 8b7034dd..9c68b70b 100644 --- a/05_safe_globals/README.md +++ b/05_safe_globals/README.md @@ -169,8 +169,7 @@ diff -uNr 04_zero_overhead_abstraction/src/bsp/rpi.rs 05_safe_globals/src/bsp/rp + // Convert newline to carrige return + newline. + if c == ' ' { -+ self.write_char(' -') ++ self.write_char(' ') } + + self.write_char(c); diff --git a/06_drivers_gpio_uart/README.md b/06_drivers_gpio_uart/README.md index b1676571..f8f39ed6 100644 --- a/06_drivers_gpio_uart/README.md +++ b/06_drivers_gpio_uart/README.md @@ -167,7 +167,7 @@ diff -uNr 05_safe_globals/src/arch.rs 06_drivers_gpio_uart/src/arch.rs diff -uNr 05_safe_globals/src/bsp/driver/bcm/bcm2xxx_gpio.rs 06_drivers_gpio_uart/src/bsp/driver/bcm/bcm2xxx_gpio.rs --- 05_safe_globals/src/bsp/driver/bcm/bcm2xxx_gpio.rs +++ 06_drivers_gpio_uart/src/bsp/driver/bcm/bcm2xxx_gpio.rs -@@ -0,0 +1,158 @@ +@@ -0,0 +1,157 @@ +// SPDX-License-Identifier: MIT +// +// Copyright (c) 2018-2019 Andre Richter @@ -271,26 +271,6 @@ diff -uNr 05_safe_globals/src/bsp/driver/bcm/bcm2xxx_gpio.rs 06_drivers_gpio_uar + fn ptr(&self) -> *const RegisterBlock { + self.base_addr as *const _ + } -+ -+ /// Map PL011 UART as standard output. -+ /// -+ /// TX to pin 14 -+ /// RX to pin 15 -+ pub fn map_pl011_uart(&mut self) { -+ // Map to pins. -+ self.GPFSEL1 -+ .modify(GPFSEL1::FSEL14::AltFunc0 + GPFSEL1::FSEL15::AltFunc0); -+ -+ // Enable pins 14 and 15. -+ self.GPPUD.set(0); -+ arch::spin_for_cycles(150); -+ -+ self.GPPUDCLK0 -+ .write(GPPUDCLK0::PUDCLK14::AssertClock + GPPUDCLK0::PUDCLK15::AssertClock); -+ arch::spin_for_cycles(150); -+ -+ self.GPPUDCLK0.set(0); -+ } +} + +//-------------------------------------------------------------------------------------------------- @@ -310,10 +290,29 @@ diff -uNr 05_safe_globals/src/bsp/driver/bcm/bcm2xxx_gpio.rs 06_drivers_gpio_uar + } + } + -+ // Only visible to other BSP code. ++ /// Map PL011 UART as standard output. ++ /// ++ /// TX to pin 14 ++ /// RX to pin 15 + pub fn map_pl011_uart(&self) { + let mut r = &self.inner; -+ r.lock(|inner| inner.map_pl011_uart()); ++ r.lock(|inner| { ++ // Map to pins. ++ inner ++ .GPFSEL1 ++ .modify(GPFSEL1::FSEL14::AltFunc0 + GPFSEL1::FSEL15::AltFunc0); ++ ++ // Enable pins 14 and 15. ++ inner.GPPUD.set(0); ++ arch::spin_for_cycles(150); ++ ++ inner ++ .GPPUDCLK0 ++ .write(GPPUDCLK0::PUDCLK14::AssertClock + GPPUDCLK0::PUDCLK15::AssertClock); ++ arch::spin_for_cycles(150); ++ ++ inner.GPPUDCLK0.set(0); ++ }) + } +} + @@ -525,8 +524,7 @@ diff -uNr 05_safe_globals/src/bsp/driver/bcm/bcm2xxx_pl011_uart.rs 06_drivers_gp + // Convert newline to carrige return + newline. + if c == ' ' { -+ self.write_char(' -') ++ self.write_char(' ') + } + + self.write_char(c); @@ -626,8 +624,7 @@ diff -uNr 05_safe_globals/src/bsp/driver/bcm/bcm2xxx_pl011_uart.rs 06_drivers_gp + let mut ret = inner.DR.get() as u8 as char; + + // Convert carrige return to newline. -+ if ret == ' -' { ++ if ret == ' ' { + ret = ' ' + } @@ -751,8 +748,7 @@ diff -uNr 05_safe_globals/src/bsp/rpi.rs 06_drivers_gpio_uart/src/bsp/rpi.rs - // Convert newline to carrige return + newline. - if c == ' ' { -- self.write_char(' -') +- self.write_char(' ') - } - - self.write_char(c); diff --git a/06_drivers_gpio_uart/kernel b/06_drivers_gpio_uart/kernel index a30957c033abd6df2a8b8504f4beff8c6833d05c..7fdc4e818625f3e717c7d74c08c804ae4463d7a6 100755 GIT binary patch delta 806 zcmZ8dF=$g!6ul?;AwN+}BMHCOLVjtQkfdruqlk(oAZRPpHsGKR8f^+ii8YGgl(Zcj zI@k}9H@Ij!lng>Zu2Z|SX#7o3>nBk~chVaVPd0nWh>hunm#8*8ecAwz zn~PMvNagGgAGLT*EtX+3ZbWdMRozGhR^mo8>ZqzHXPYIZx;0D25ZiVmgpbUxLJJ2K z3J|4RF|;Gqrnwf?6Gq*6l9|t|()r2(Ds>eU0E3cFeUX zmfXV=-1|WSHN7@Va$gC2ywgVHtbYXlVZV*1h4_fie18n*6(u}=G|3u+2;zhl%p)lj fylgdtvZJoF@~My%8rqZdz&_SlOH zk>}Arl*EfcWrKL|ApYE1Ey03^CI`t$ukFE~m)-X+eTR87-^@2N-+S$)V0$T8tK$)h z_aEbl(H(Pk65V?<>z)C6!2?9}@($GsRLeT=)eD_>(m2l?4f#kn>+~~9Lr1O9UkEgMi{u<*YrHPm9`MOp)suFkr=q#8 z>dmfdG{XUk5ZRjvP{hsaNW!(ZVIJ;>5PpQCC#FxGJzc7nOY>HxSf0DMC&U-!=P7H& z5HEa=>0Y?QvqT*cL&SyR&B|=4TD@&e&sjO5N!_paEs?zUX})J`Zgv+g8^$@WfkF=% z7iZ4Myl6{x&jHzjC-L2U5k&#X`XP~cA#hnQ=iX)elQ4}3>Yz^Hs#fAK(PqU2%%~J6 zo6DU#tjkG`6HnXCwO%7V!|rR1XyNO1s- zU|`?_lMD>!pnRYk!N5Jh(?2M&xF9LDsHjpQAXC8@B5uI}(FY+J7+|yvR9uH+vzGKR FW&lNtPBs7l delta 288 zcmexh`@wd?LdL|2ixzV})Sf8Hz%XHJ(q=!#N32E+3=A6@85)8Z8nh-JV2;1`fLUG( zME`GQy!cO>;pa03hA9fn3|lyXdR{0qOw`;s*^6DCF>!JhyBcHYhaxqvPNf+dqTO34SEkm3OI z_`oCs!!; *const RegisterBlock { self.base_addr as *const _ } - - /// Map PL011 UART as standard output. - /// - /// TX to pin 14 - /// RX to pin 15 - pub fn map_pl011_uart(&mut self) { - // Map to pins. - self.GPFSEL1 - .modify(GPFSEL1::FSEL14::AltFunc0 + GPFSEL1::FSEL15::AltFunc0); - - // Enable pins 14 and 15. - self.GPPUD.set(0); - arch::spin_for_cycles(150); - - self.GPPUDCLK0 - .write(GPPUDCLK0::PUDCLK14::AssertClock + GPPUDCLK0::PUDCLK15::AssertClock); - arch::spin_for_cycles(150); - - self.GPPUDCLK0.set(0); - } } //-------------------------------------------------------------------------------------------------- @@ -140,10 +120,29 @@ impl GPIO { } } - // Only visible to other BSP code. + /// Map PL011 UART as standard output. + /// + /// TX to pin 14 + /// RX to pin 15 pub fn map_pl011_uart(&self) { let mut r = &self.inner; - r.lock(|inner| inner.map_pl011_uart()); + r.lock(|inner| { + // Map to pins. + inner + .GPFSEL1 + .modify(GPFSEL1::FSEL14::AltFunc0 + GPFSEL1::FSEL15::AltFunc0); + + // Enable pins 14 and 15. + inner.GPPUD.set(0); + arch::spin_for_cycles(150); + + inner + .GPPUDCLK0 + .write(GPPUDCLK0::PUDCLK14::AssertClock + GPPUDCLK0::PUDCLK15::AssertClock); + arch::spin_for_cycles(150); + + inner.GPPUDCLK0.set(0); + }) } } diff --git a/07_uart_chainloader/README.md b/07_uart_chainloader/README.md index 02a1a315..6ceac950 100644 --- a/07_uart_chainloader/README.md +++ b/07_uart_chainloader/README.md @@ -189,8 +189,7 @@ diff -uNr 06_drivers_gpio_uart/src/bsp/driver/bcm/bcm2xxx_pl011_uart.rs 07_uart_ + } - // Convert carrige return to newline. -- if ret == ' -' { +- if ret == ' ' { - ret = ' ' + fn clear(&self) { diff --git a/07_uart_chainloader/kernel b/07_uart_chainloader/kernel index 202ca3d96d2bc8eeec4e6955c67841be9a02f8b5..0297e9fbd5b899501151cfd07509ac7ed44f7380 100755 GIT binary patch delta 2995 zcmZ`)YfMx}6h7zPy>J&$!9oF{E(<8IJY;z-V5_?&h^SRSnkY>QDAs2ih&CbV4=~oo zwl?*qkdYrvC9O@Nk=kmq@}u<`lN!=OLWxcK08A^Ewo1~pu2HvV?wvu{=uLKK?sv}l z<~wK3%$@4drh2r_E=*3^p+Hv(q>KhDlo30?a0LCbe44SYSL^oRQmvV$zU~IBQfjli zKgKd#-u*LXYTGo!*~B6cE3k=eMD$q0QuYaABF(?Cpm!8p!lD&SjOi{gi2B&N+H3=9 z2?{P(a1(iw%WUwtf(vkf{jH#bhJ`A|7Y}#?4)hKNg28x4iu%J5de;-ZgK=@%=6eWT z=M~uN3kK^s{yKEl#UTtH8DI@6I(Vq{`Y7b42x$VS=X9Kwhwi3OyA?V>p|tpSG}y^v zd9Z)yzb>_zPOEH~L@6}b@TFYx^@oAM#n}L2=ZZ~;v2E_Al^v=S%O-7D(vb(y1yl@Z z(u`QL>v*CLaP=7955iBY+%{BTG;5u8+sDI<$wOc)6#K>P2T3)&SzugH8^^{~hl`K$ zr&H{^Hp;5c8*pjf!98)Yg)R*Szg^r}7eQEKH|!bA(qM)Qy+{@0U?d!`;|}Y4V4h7U zn}aY(9#nCJFEF7(zfK)8u7aV2b=EyhQ~O@jpo{PD_zj>I2{$Im*20`&m>fMf6+*|@ z3t@O8F6uD>Nvtv)&)_HvgyS^!u-|m5x4|?!da<3YvEwValby0-zLx6?WVzX-9X+{O zzJRP=@DPqX%!a^ERN)jA&QfO|n@R&Ct2djs;qba<_HqQqXEy7`A1fdb>`?o-*75CV z+)7jWGO4h)DuCv;K3??o?8695=%7rk-X%}6@~Eju2=GeiPTiQwQ2KQ2tefhvqRMDX z#~%cXp0t$%TpVq+p6>0NRIz_t)%zz@d%tFbSO9Mz5h0dWob&UenWGm|vSq%&YSgDM zQ3rF-d_N3#Id+-0(f1(8I4R4F#4Grg|F1|q8*QtqsounTlks`~&1BqdW35h1$ZFMs zt4JFVzxl|qUf?Za+{eCjVth=p-Ez+n;}EMQnB8%r?kWm7XT;< zf=n-37%mB1`pYtmG9wkANmAjMbN)IVW}pf+%(ool6Sstz-!{z(oMdfe#$D_nslt7% zm)@#n&84VmbAoU{)LP6!Td|mEw3S!;Cp=%Us@|=H@vbU~X=%5z=Hz zw;};h;nJGPoV81sGX?ppQQZ6}VTm`eUUJ7ab6~?6s3)EYseP+Sp~5*U+aWVs_i#v7 zM}+#JkgVnG*!r!4j8Uc3*V1#KQ%T=zObJxG_o?Hi#o317ZX&kC()s7Pvfa z5>FzWcYsVlc1DfBrO+#8z)FD6gh47T6-*B$kr0$1@Ot{}@C7z7w~GoW3-YWmFE@Kg zh3jH7@&&Ffv|3N*AzShzfy+GB3jZHz85_(5#p~>Fdp=H`As&s5xX_VxI%I>6F0$5@ zc)f5>V!b3E-RxpEeLHkEk&RWp1aXf@&JWB9f^GKRu`DM@JwHbh9~J>6riQJfA?~uN zrb6)d>ELl1=}*_X`8Wl=^d~p-*}x`pa0PC&q_;9>4mvtQ?@GDYqr1`yZl_M*`zHNm zW1JGW^yl9r{`^XXiaG_nf27XsAUbSJkf5weF5f8Jig?PTY zfJhe8qESiK9VwgWGU3snfxN&4Hw>FNzwYPXse74GM9uaU6^7H@U1FJK!R`sXW|4(^ z1>fcv%U{x^3%r5wXv#uMnr;Zd}wx91fA{S`8IImY=TJ(!AqPbp?7 zw)B=fw~3<19N2s1n7}^wU>f_h1Z({#%WYu0s)(e6vOwi}x;Hl_?FUyhNCX|f?GPSh|FGecra zkYvJid%AhSzd$5${2?Sxn?^GjPJ>3tNR;>yk`6QsLE`*FsfpBc-@A9PCER2?@BV)0 zoO{0R?c`By@~9RWKzGgy3Jl~y-uKA{<&qs>JeB_Zqnh62wGLKct~NoRql0bOsFars zp1^7>8@z%(?W(4G<17`i0pn}~VwEX!*$0R&`W`W%Lkccr4h3D#gB3ct?r$nD(UFcI z;~E7wk|wE48^;x#gCp#=f*ulcRm=*F)FnJv7fU3QS)M%ghaTG7Ty?R`Ol|YO2m@yo z*j1lQws3qeM4B@ZVm%|QO+^nkHMjRnt_zb6fEMnKyXB^xWNJ4}KO$2){2~cEF{TFl zd*(LRVkp&GFo#lTv)~h@q#Lz@&V#c6WZWNYw$rkCkWTifGFW!if|cP)fB~RlKwQ(^ z#M|&#GvLb0ydQ+0Q91W{g}zOTG;i-n(XSo=eXi)&Iko+=jdeLX+YoJv^xAjJF{ zOz}iU$pOdG;7Bv)A3Hjevk~VZOgc}hc!>u$p~5K}O;B6~U9m=*?=Dh@)@v}pCm?<; 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- - // Enable pins 14 and 15. - self.GPPUD.set(0); - arch::spin_for_cycles(150); - - self.GPPUDCLK0 - .write(GPPUDCLK0::PUDCLK14::AssertClock + GPPUDCLK0::PUDCLK15::AssertClock); - arch::spin_for_cycles(150); - - self.GPPUDCLK0.set(0); - } } //-------------------------------------------------------------------------------------------------- @@ -140,10 +120,29 @@ impl GPIO { } } - // Only visible to other BSP code. + /// Map PL011 UART as standard output. + /// + /// TX to pin 14 + /// RX to pin 15 pub fn map_pl011_uart(&self) { let mut r = &self.inner; - r.lock(|inner| inner.map_pl011_uart()); + r.lock(|inner| { + // Map to pins. + inner + .GPFSEL1 + .modify(GPFSEL1::FSEL14::AltFunc0 + GPFSEL1::FSEL15::AltFunc0); + + // Enable pins 14 and 15. + inner.GPPUD.set(0); + arch::spin_for_cycles(150); + + inner + .GPPUDCLK0 + .write(GPPUDCLK0::PUDCLK14::AssertClock + GPPUDCLK0::PUDCLK15::AssertClock); + arch::spin_for_cycles(150); + + inner.GPPUDCLK0.set(0); + }) } } diff --git a/08_timestamps/README.md b/08_timestamps/README.md index 0f77b008..760071bc 100644 --- a/08_timestamps/README.md +++ b/08_timestamps/README.md @@ -237,8 +237,7 @@ diff -uNr 07_uart_chainloader/src/bsp/driver/bcm/bcm2xxx_pl011_uart.rs 08_timest + let mut ret = inner.DR.get() as u8 as char; + + // Convert carrige return to newline. -+ if ret == ' -' { ++ if ret == ' ' { + ret = ' ' + } diff --git a/08_timestamps/kernel b/08_timestamps/kernel index 95064d3b306b8c602d5f25e3b6099c3469525a39..3bfb485adb3cd89f64e2bb3e468e140095015b4d 100755 GIT binary patch delta 556 zcmXYtJuE{}7>3V#L;OZtN_!VgL#UsmZky_@l=L>l^|KJcCS5RCNC$%iqe(h_CecVV z79kNwOu8@_urUcSkQmy0gbELDQHWmUKwMte19^SV9xMCsEKN zO_DlLRG*@T_?nw7s#0uA9ct5Ni*Y?f>Yu;MyuvXmWMv?WX#3D zcG_f8vuf~1$AZ#hE-7y)S?n#J1In9nQOS%+ce|2XsAS3oft%so9w|pFr2fmj(|EVm m4}|&$Lcu^d7#SKAbEq#6=K3O*YxwpmGN>*zsyuRb!u<~#5oOH) diff --git a/08_timestamps/src/bsp/driver/bcm/bcm2xxx_gpio.rs b/08_timestamps/src/bsp/driver/bcm/bcm2xxx_gpio.rs index dfbcc58f..a9ceda61 100644 --- a/08_timestamps/src/bsp/driver/bcm/bcm2xxx_gpio.rs +++ b/08_timestamps/src/bsp/driver/bcm/bcm2xxx_gpio.rs @@ -101,26 +101,6 @@ impl GPIOInner { fn ptr(&self) -> *const RegisterBlock { self.base_addr as *const _ } - - /// Map PL011 UART as standard output. - /// - /// TX to pin 14 - /// RX to pin 15 - pub fn map_pl011_uart(&mut self) { - // Map to pins. - self.GPFSEL1 - .modify(GPFSEL1::FSEL14::AltFunc0 + GPFSEL1::FSEL15::AltFunc0); - - // Enable pins 14 and 15. - self.GPPUD.set(0); - arch::spin_for_cycles(150); - - self.GPPUDCLK0 - .write(GPPUDCLK0::PUDCLK14::AssertClock + GPPUDCLK0::PUDCLK15::AssertClock); - arch::spin_for_cycles(150); - - self.GPPUDCLK0.set(0); - } } //-------------------------------------------------------------------------------------------------- @@ -140,10 +120,29 @@ impl GPIO { } } - // Only visible to other BSP code. + /// Map PL011 UART as standard output. + /// + /// TX to pin 14 + /// RX to pin 15 pub fn map_pl011_uart(&self) { let mut r = &self.inner; - r.lock(|inner| inner.map_pl011_uart()); + r.lock(|inner| { + // Map to pins. + inner + .GPFSEL1 + .modify(GPFSEL1::FSEL14::AltFunc0 + GPFSEL1::FSEL15::AltFunc0); + + // Enable pins 14 and 15. + inner.GPPUD.set(0); + arch::spin_for_cycles(150); + + inner + .GPPUDCLK0 + .write(GPPUDCLK0::PUDCLK14::AssertClock + GPPUDCLK0::PUDCLK15::AssertClock); + arch::spin_for_cycles(150); + + inner.GPPUDCLK0.set(0); + }) } }