From d2636fc9ba139f161fceb78c8eb8b53b58d7e3d1 Mon Sep 17 00:00:00 2001
From: Andre Richter <andre.o.richter@gmail.com>
Date: Mon, 2 Apr 2018 19:08:54 +0200
Subject: [PATCH] Add compiler fence before mailbox signaling

---
 05_uart0/kernel8.img | Bin 2080 -> 2080 bytes
 05_uart0/src/main.rs |   7 +++++++
 05_uart0/src/uart.rs |   6 ++++++
 3 files changed, 13 insertions(+)

diff --git a/05_uart0/kernel8.img b/05_uart0/kernel8.img
index 54459f9ac6a1afec18c31db9b0b5bdafa3a3640f..646ae32d2a696e5d0a833ebbb7613128147d7f62 100755
GIT binary patch
delta 393
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z1Wj)|T*9p&Xgs69P8!UiTztKU)A#?r@BjY%zSjsfLJvvaYNO|2Inb&>#Xw@kaCoS8
zc_|V8XqIjOu7ptC5S(V|@F!jEE&E%3fQ#6dt+FbA+o~{iY6#RTaey5k+><z9H>-^@
z^BO*bzYQtIzcT$qNUBG({oJCmEdxdX5w_c7<}5Ybk>8ZgX*e4M(UPI4A1#P7A-Oy!
z6uM)QbA1}_^PH0BrVF<L$eBpP=bnmT&PLWv1h_-ttxLeV7m6&{rf*%JsF<}GPdH;;
z1Mcr=qX5O$2DZxT=BKT?tDu-$6q%P4a|y7?(Zm(n`=W}u1~{=x`{d*_Mp`@Y90y;<
zq~4<_77_|4wSgy`>d;9ys$pjzRpW%}xrvTZ&9R?)ld5d@&VwS*%ZFvXMcU{w?d_s}
D%yyQF

delta 393
zcmX9)JxD@P6h7}=%|9aZryz@`)nrpINE*avH0kzqH)(s;psRr<4Pr~CB(!KP_Jkm4
z@s6)4YKmxAD6kg|B~mTj&a2_$ewXu|?|kR9oGs_&GAR&pKT6ouVcwy-$4YV?in7<)
zka<^8?h&Z=i4b%@wR0YXx7W^{0Mu;&hjxVjMGHsYv~c+&QXMVW)B+E*XMqd00Q7uD
zqGkA675wDU;5Uqg2Iyzw=0tTKC;{*owe%=1eRojMVV|K6FVXloxC#Nt#&%|1QO1%f
z&YI!y)h!ZzC7hVz9GN{kBrB*rFcoFR>shJb;9CsbJOUasL)I|X{(4+ur8a4DZ|F-P
zHjjZSQ$Tehh|0RqRXFS}30>Xd6P0VB8{EV{IvJ}u5YoFAPCsj59TOUB)wWH$YY#uH
zF~ArF-kLe(A<3aIurE~4c)ZsZU%kV6-zQOnFEZrQ|2$9&nB5b2InOX3S4WAM$_TlN
HnEU)MCSR2}

diff --git a/05_uart0/src/main.rs b/05_uart0/src/main.rs
index 2e82856f..8b6c1d12 100644
--- a/05_uart0/src/main.rs
+++ b/05_uart0/src/main.rs
@@ -35,6 +35,8 @@ mod mbox;
 mod gpio;
 mod uart;
 
+use core::sync::atomic::{compiler_fence, Ordering};
+
 fn main() {
     let mut mbox = mbox::Mbox::new();
     let uart = uart::Uart::new();
@@ -54,6 +56,11 @@ fn main() {
     mbox.buffer[6] = 0;
     mbox.buffer[7] = mbox::tag::LAST;
 
+    // Insert a compiler fence that ensures that all stores to the
+    // mbox buffer are finished before the GPU is signaled (which is
+    // done by a store operation as well).
+    compiler_fence(Ordering::SeqCst);
+
     // send the message to the GPU and receive answer
     let serial_avail = match mbox.call(mbox::channel::PROP) {
         Err(_) => false,
diff --git a/05_uart0/src/uart.rs b/05_uart0/src/uart.rs
index cb9c4df5..a724c8df 100644
--- a/05_uart0/src/uart.rs
+++ b/05_uart0/src/uart.rs
@@ -26,6 +26,7 @@ use super::MMIO_BASE;
 use volatile_register::*;
 use mbox;
 use gpio;
+use core::sync::atomic::{compiler_fence, Ordering};
 
 const UART_BASE: u32 = MMIO_BASE + 0x201000;
 
@@ -77,6 +78,11 @@ impl Uart {
         mbox.buffer[7] = 0; // skip turbo setting
         mbox.buffer[8] = mbox::tag::LAST;
 
+        // Insert a compiler fence that ensures that all stores to the
+        // mbox buffer are finished before the GPU is signaled (which
+        // is done by a store operation as well).
+        compiler_fence(Ordering::SeqCst);
+
         if let Err(_) = mbox.call(mbox::channel::PROP) {
             return Err(UartError::MailboxError); // Abort if UART clocks couldn't be set
         };