diff --git a/03_uart1/src/gpio.rs b/03_uart1/src/gpio.rs
index 9db608e8..65bf7f0a 100644
--- a/03_uart1/src/gpio.rs
+++ b/03_uart1/src/gpio.rs
@@ -22,8 +22,8 @@
  * SOFTWARE.
  */
 
-use volatile_register::RW;
 use super::MMIO_BASE;
+use volatile_register::RW;
 
 pub const GPFSEL1: *const RW<u32> = (MMIO_BASE + 0x0020_0004) as *const RW<u32>;
 pub const GPPUD: *const RW<u32> = (MMIO_BASE + 0x0020_0094) as *const RW<u32>;
diff --git a/03_uart1/src/uart.rs b/03_uart1/src/uart.rs
index 1c67f3c8..21555567 100644
--- a/03_uart1/src/uart.rs
+++ b/03_uart1/src/uart.rs
@@ -23,8 +23,8 @@
  */
 
 use super::MMIO_BASE;
-use volatile_register::*;
 use gpio;
+use volatile_register::*;
 
 const MINI_UART_BASE: u32 = MMIO_BASE + 0x21_5000;
 
diff --git a/04_mailboxes/src/gpio.rs b/04_mailboxes/src/gpio.rs
index 9db608e8..65bf7f0a 100644
--- a/04_mailboxes/src/gpio.rs
+++ b/04_mailboxes/src/gpio.rs
@@ -22,8 +22,8 @@
  * SOFTWARE.
  */
 
-use volatile_register::RW;
 use super::MMIO_BASE;
+use volatile_register::RW;
 
 pub const GPFSEL1: *const RW<u32> = (MMIO_BASE + 0x0020_0004) as *const RW<u32>;
 pub const GPPUD: *const RW<u32> = (MMIO_BASE + 0x0020_0094) as *const RW<u32>;
diff --git a/04_mailboxes/src/main.rs b/04_mailboxes/src/main.rs
index 5fa2e798..9a4a942f 100644
--- a/04_mailboxes/src/main.rs
+++ b/04_mailboxes/src/main.rs
@@ -30,8 +30,8 @@ extern crate volatile_register;
 
 const MMIO_BASE: u32 = 0x3F00_0000;
 
-mod mbox;
 mod gpio;
+mod mbox;
 mod uart;
 
 use core::sync::atomic::{compiler_fence, Ordering};
diff --git a/04_mailboxes/src/uart.rs b/04_mailboxes/src/uart.rs
index 49d2a39a..77a12ff1 100644
--- a/04_mailboxes/src/uart.rs
+++ b/04_mailboxes/src/uart.rs
@@ -23,8 +23,8 @@
  */
 
 use super::MMIO_BASE;
-use volatile_register::*;
 use gpio;
+use volatile_register::*;
 
 const MINI_UART_BASE: u32 = MMIO_BASE + 0x21_5000;
 
diff --git a/05_uart0/src/gpio.rs b/05_uart0/src/gpio.rs
index 9db608e8..65bf7f0a 100644
--- a/05_uart0/src/gpio.rs
+++ b/05_uart0/src/gpio.rs
@@ -22,8 +22,8 @@
  * SOFTWARE.
  */
 
-use volatile_register::RW;
 use super::MMIO_BASE;
+use volatile_register::RW;
 
 pub const GPFSEL1: *const RW<u32> = (MMIO_BASE + 0x0020_0004) as *const RW<u32>;
 pub const GPPUD: *const RW<u32> = (MMIO_BASE + 0x0020_0094) as *const RW<u32>;
diff --git a/05_uart0/src/main.rs b/05_uart0/src/main.rs
index cd0ad5c5..37b4c263 100644
--- a/05_uart0/src/main.rs
+++ b/05_uart0/src/main.rs
@@ -30,8 +30,8 @@ extern crate volatile_register;
 
 const MMIO_BASE: u32 = 0x3F00_0000;
 
-mod mbox;
 mod gpio;
+mod mbox;
 mod uart;
 
 use core::sync::atomic::{compiler_fence, Ordering};
diff --git a/05_uart0/src/uart.rs b/05_uart0/src/uart.rs
index 0e9f6de2..522bb2dc 100644
--- a/05_uart0/src/uart.rs
+++ b/05_uart0/src/uart.rs
@@ -23,10 +23,10 @@
  */
 
 use super::MMIO_BASE;
-use volatile_register::*;
-use mbox;
-use gpio;
 use core::sync::atomic::{compiler_fence, Ordering};
+use gpio;
+use mbox;
+use volatile_register::*;
 
 const UART_BASE: u32 = MMIO_BASE + 0x20_1000;
 
diff --git a/06_raspbootin64/src/gpio.rs b/06_raspbootin64/src/gpio.rs
index 9db608e8..65bf7f0a 100644
--- a/06_raspbootin64/src/gpio.rs
+++ b/06_raspbootin64/src/gpio.rs
@@ -22,8 +22,8 @@
  * SOFTWARE.
  */
 
-use volatile_register::RW;
 use super::MMIO_BASE;
+use volatile_register::RW;
 
 pub const GPFSEL1: *const RW<u32> = (MMIO_BASE + 0x0020_0004) as *const RW<u32>;
 pub const GPPUD: *const RW<u32> = (MMIO_BASE + 0x0020_0094) as *const RW<u32>;