Add minimal JTAG boot
Andre Richter
5 years ago
committed by
Andre Richter
parent
36ab2efbd6
commit
8da8c0e33f
@ -0,0 +1,6 @@
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[target.aarch64-unknown-none]
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rustflags = [
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"-C", "link-arg=-Tlink.ld",
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"-C", "target-feature=-fp-armv8",
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"-C", "target-cpu=cortex-a53",
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]
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@ -0,0 +1,57 @@
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# This file is automatically @generated by Cargo.
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# It is not intended for manual editing.
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[[package]]
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name = "cortex-a"
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version = "2.3.1"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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dependencies = [
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"register 0.3.2 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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[[package]]
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name = "jtag_boot"
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version = "0.1.0"
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dependencies = [
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"cortex-a 2.3.1 (registry+https://github.com/rust-lang/crates.io-index)",
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"raspi3_boot 0.1.0",
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"register 0.3.2 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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[[package]]
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name = "panic-abort"
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version = "0.3.1"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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[[package]]
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name = "r0"
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version = "0.2.2"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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[[package]]
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name = "raspi3_boot"
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version = "0.1.0"
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dependencies = [
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"cortex-a 2.3.1 (registry+https://github.com/rust-lang/crates.io-index)",
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"panic-abort 0.3.1 (registry+https://github.com/rust-lang/crates.io-index)",
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"r0 0.2.2 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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[[package]]
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name = "register"
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version = "0.3.2"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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dependencies = [
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"tock-registers 0.3.0 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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[[package]]
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name = "tock-registers"
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version = "0.3.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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[metadata]
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"checksum cortex-a 2.3.1 (registry+https://github.com/rust-lang/crates.io-index)" = "12425c4491f31f28f539c74382ade69ee9db4f1f597aa177f43e072595562e46"
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"checksum panic-abort 0.3.1 (registry+https://github.com/rust-lang/crates.io-index)" = "2c14a66511ed17b6a8b4256b868d7fd207836d891db15eea5195dbcaf87e630f"
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"checksum r0 0.2.2 (registry+https://github.com/rust-lang/crates.io-index)" = "e2a38df5b15c8d5c7e8654189744d8e396bddc18ad48041a500ce52d6948941f"
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"checksum register 0.3.2 (registry+https://github.com/rust-lang/crates.io-index)" = "a0f44a6dc9a98359515541a0c46ef4e3630a30879c1d7a4038f31dd533570bfb"
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"checksum tock-registers 0.3.0 (registry+https://github.com/rust-lang/crates.io-index)" = "c758f5195a2e0df9d9fecf6f506506b2766ff74cf64db1e995c87e2761a5c3e2"
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@ -0,0 +1,13 @@
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[package]
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name = "jtag_boot"
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version = "0.1.0"
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authors = ["Andre Richter <andre.o.richter@gmail.com>"]
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edition = "2018"
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[dependencies]
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raspi3_boot = { path = "raspi3_boot" }
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cortex-a = "2.3.1"
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register = "0.3.2"
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[package.metadata.cargo-xbuild]
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sysroot_path = "../xbuild_sysroot"
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@ -0,0 +1,65 @@
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#
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# MIT License
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#
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# Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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# copies of the Software, and to permit persons to whom the Software is
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# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in all
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# copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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# SOFTWARE.
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#
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TARGET = aarch64-unknown-none
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SOURCES = $(wildcard **/*.rs) $(wildcard **/*.S) link.ld
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OBJCOPY = cargo objcopy --
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OBJCOPY_PARAMS = --strip-all -O binary
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UTILS_CONTAINER = andrerichter/raspi3-utils
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DOCKER_CMD = docker run -it --rm -v $(shell pwd):/work -w /work
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DOCKER_TTY = --privileged -v /dev:/dev
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QEMU_CMD = qemu-system-aarch64 -M raspi3 -kernel jtag_boot.img
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RASPBOOT_CMD = raspbootcom /dev/ttyUSB0 jtag_boot.img
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.PHONY: all qemu raspboot clippy clean objdump nm
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all: clean jtag_boot.img
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target/$(TARGET)/release/jtag_boot: $(SOURCES)
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cargo xbuild --target=$(TARGET) --release
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jtag_boot.img: target/$(TARGET)/release/jtag_boot
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cp $< .
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$(OBJCOPY) $(OBJCOPY_PARAMS) $< jtag_boot.img
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qemu: all
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$(DOCKER_CMD) $(UTILS_CONTAINER) $(QEMU_CMD) -serial null -serial stdio
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raspboot: all
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$(DOCKER_CMD) $(DOCKER_TTY) $(UTILS_CONTAINER) $(RASPBOOT_CMD)
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clippy:
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cargo xclippy --target=$(TARGET)
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clean:
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cargo clean
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objdump:
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cargo objdump --target $(TARGET) -- -disassemble -print-imm-hex jtag_boot
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nm:
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cargo nm --target $(TARGET) -- jtag_boot | sort
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@ -0,0 +1,4 @@
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# Xtra 1 - JTAG boot
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Not much is happening here. The binary configures the RPi's GPIO pins for `JTAG`
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mode and waits for a debugger to connect.
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Binary file not shown.
Binary file not shown.
@ -0,0 +1,55 @@
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/*
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* MIT License
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*
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* Copyright (c) 2018 Andre Richter <andre.o.richter@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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ENTRY(_boot_cores);
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SECTIONS
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{
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. = 0x80000;
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.text :
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{
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KEEP(*(.text.boot)) *(.text .text.*)
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}
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.rodata :
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{
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*(.rodata .rodata.*)
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}
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.data :
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{
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*(.data .data.*)
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}
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.bss ALIGN(8):
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{
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__bss_start = .;
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*(.bss .bss.*)
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*(COMMON)
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__bss_end = .;
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}
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/DISCARD/ : { *(.comment) *(.gnu*) *(.note*) *(.eh_frame*) }
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}
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@ -0,0 +1,10 @@
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[package]
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name = "raspi3_boot"
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version = "0.1.0"
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authors = ["Andre Richter <andre.o.richter@gmail.com>"]
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edition = "2018"
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[dependencies]
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cortex-a = "2.3.1"
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panic-abort = "0.3.1"
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r0 = "0.2.2"
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@ -0,0 +1,90 @@
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/*
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* MIT License
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*
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* Copyright (c) 2018 Jorge Aparicio
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* Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#![deny(missing_docs)]
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#![deny(warnings)]
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#![no_std]
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//! Low-level boot of the Raspberry's processor
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extern crate panic_abort;
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/// Type check the user-supplied entry function.
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#[macro_export]
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macro_rules! entry {
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($path:path) => {
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#[export_name = "main"]
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pub unsafe fn __main() -> ! {
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// type check the given path
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let f: fn() -> ! = $path;
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f()
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}
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};
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}
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/// Reset function.
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///
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/// Initializes the bss section before calling into the user's `main()`.
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unsafe fn reset() -> ! {
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extern "C" {
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// Boundaries of the .bss section, provided by the linker script
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static mut __bss_start: u64;
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static mut __bss_end: u64;
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}
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// Zeroes the .bss section
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r0::zero_bss(&mut __bss_start, &mut __bss_end);
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extern "Rust" {
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fn main() -> !;
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}
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main();
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}
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/// Entrypoint of the processor.
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///
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/// Parks all cores except core0, and then jumps to the internal
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/// `reset()` function.
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#[link_section = ".text.boot"]
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#[no_mangle]
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pub unsafe extern "C" fn _boot_cores() -> ! {
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use cortex_a::{asm, regs::*};
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const CORE_0: u64 = 0;
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const CORE_MASK: u64 = 0x3;
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const STACK_START: u64 = 0x80_000;
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if CORE_0 == MPIDR_EL1.get() & CORE_MASK {
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SP.set(STACK_START);
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reset()
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} else {
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// if not core0, infinitely wait for events
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loop {
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asm::wfe();
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}
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}
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}
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@ -0,0 +1,166 @@
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/*
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* MIT License
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*
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* Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
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* Copyright (c) 2019 Nao Taco <naotaco@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
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* SOFTWARE.
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*/
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use core::ops;
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use register::{mmio::ReadWrite, register_bitfields};
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// Descriptions taken from
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// https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
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register_bitfields! {
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u32,
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/// GPIO Function Select 1
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GPFSEL1 [
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/// Pin 15
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FSEL15 OFFSET(15) NUMBITS(3) [
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Input = 0b000,
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Output = 0b001,
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RXD0 = 0b100, // UART0 - Alternate function 0
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RXD1 = 0b010 // Mini UART - Alternate function 5
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],
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/// Pin 14
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FSEL14 OFFSET(12) NUMBITS(3) [
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Input = 0b000,
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Output = 0b001,
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TXD0 = 0b100, // UART0 - Alternate function 0
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TXD1 = 0b010 // Mini UART - Alternate function 5
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]
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],
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/// GPIO Function Select 2
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GPFSEL2 [
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/// Pin 27
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FSEL27 OFFSET(21) NUMBITS(3)[
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Input = 0b000,
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Output = 0b001,
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ARM_TMS = 0b011 // JTAG TMS - Alternate function 4
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],
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/// Pin 26
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FSEL26 OFFSET(18) NUMBITS(3)[
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Input = 0b000,
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Output = 0b001,
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ARM_TDI = 0b011 // JTAG TDI - Alternate function 4
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],
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/// Pin 25
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FSEL25 OFFSET(15) NUMBITS(3)[
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Input = 0b000,
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Output = 0b001,
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ARM_TCK = 0b011 // JTAG TCK - Alternate function 4
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],
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/// Pin 24
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FSEL24 OFFSET(12) NUMBITS(3)[ // GPIO24
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Input = 0b000,
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Output = 0b001,
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ARM_TDO = 0b011 // JTAG TDO - Alternate function 4
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],
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/// Pin 23
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FSEL23 OFFSET(9) NUMBITS(3)[
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Input = 0b000,
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Output = 0b001,
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ARM_RTCK = 0b011 // JTAG RTCK - Alternate function 4
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],
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/// Pin 22
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FSEL22 OFFSET(6) NUMBITS(3)[
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Input = 0b000,
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Output = 0b001,
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ARM_TRST = 0b011 // JTAG TRST - Alternate function 4
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]
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],
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/// GPIO Pull-up/down Clock Register 0
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GPPUDCLK0 [
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/// Pin 15
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PUDCLK15 OFFSET(15) NUMBITS(1) [
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NoEffect = 0,
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AssertClock = 1
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],
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/// Pin 14
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PUDCLK14 OFFSET(14) NUMBITS(1) [
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NoEffect = 0,
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AssertClock = 1
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]
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]
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}
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#[allow(non_snake_case)]
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#[repr(C)]
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pub struct RegisterBlock {
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pub GPFSEL0: ReadWrite<u32>, // 0x00
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pub GPFSEL1: ReadWrite<u32, GPFSEL1::Register>, // 0x04
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pub GPFSEL2: ReadWrite<u32, GPFSEL2::Register>, // 0x08
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pub GPFSEL3: ReadWrite<u32>, // 0x0C
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pub GPFSEL4: ReadWrite<u32>, // 0x10
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pub GPFSEL5: ReadWrite<u32>, // 0x14
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__reserved_0: u32, // 0x18
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GPSET0: ReadWrite<u32>, // 0x1C
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GPSET1: ReadWrite<u32>, // 0x20
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__reserved_1: u32, //
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GPCLR0: ReadWrite<u32>, // 0x28
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__reserved_2: [u32; 2], //
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GPLEV0: ReadWrite<u32>, // 0x34
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GPLEV1: ReadWrite<u32>, // 0x38
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__reserved_3: u32, //
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GPEDS0: ReadWrite<u32>, // 0x40
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GPEDS1: ReadWrite<u32>, // 0x44
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__reserved_4: [u32; 7], //
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GPHEN0: ReadWrite<u32>, // 0x64
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GPHEN1: ReadWrite<u32>, // 0x68
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__reserved_5: [u32; 10], //
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pub GPPUD: ReadWrite<u32>, // 0x94
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pub GPPUDCLK0: ReadWrite<u32, GPPUDCLK0::Register>, // 0x98
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pub GPPUDCLK1: ReadWrite<u32>, // 0x9C
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}
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||||
/// Public interface to the GPIO MMIO area
|
||||
pub struct GPIO {
|
||||
base_addr: usize,
|
||||
}
|
||||
|
||||
impl ops::Deref for GPIO {
|
||||
type Target = RegisterBlock;
|
||||
|
||||
fn deref(&self) -> &Self::Target {
|
||||
unsafe { &*self.ptr() }
|
||||
}
|
||||
}
|
||||
|
||||
impl GPIO {
|
||||
pub fn new(base_addr: usize) -> GPIO {
|
||||
GPIO { base_addr }
|
||||
}
|
||||
|
||||
/// Returns a pointer to the register block
|
||||
fn ptr(&self) -> *const RegisterBlock {
|
||||
self.base_addr as *const _
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,65 @@
|
||||
/*
|
||||
* MIT License
|
||||
*
|
||||
* Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*/
|
||||
|
||||
#![no_std]
|
||||
#![no_main]
|
||||
|
||||
const MMIO_BASE: usize = 0x3F00_0000;
|
||||
const GPIO_BASE: usize = MMIO_BASE + 0x0020_0000;
|
||||
const MINI_UART_BASE: usize = MMIO_BASE + 0x0021_5000;
|
||||
|
||||
mod gpio;
|
||||
mod mini_uart;
|
||||
|
||||
pub fn setup_jtag(gpio: &gpio::GPIO) {
|
||||
gpio.GPFSEL2.modify(
|
||||
gpio::GPFSEL2::FSEL27::ARM_TMS
|
||||
+ gpio::GPFSEL2::FSEL26::ARM_TDI
|
||||
+ gpio::GPFSEL2::FSEL25::ARM_TCK
|
||||
+ gpio::GPFSEL2::FSEL24::ARM_TDO
|
||||
+ gpio::GPFSEL2::FSEL23::ARM_RTCK
|
||||
+ gpio::GPFSEL2::FSEL22::ARM_TRST,
|
||||
);
|
||||
}
|
||||
|
||||
fn kernel_entry() -> ! {
|
||||
let gpio = gpio::GPIO::new(GPIO_BASE);
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Instantiate MiniUart
|
||||
//------------------------------------------------------------
|
||||
let mini_uart = mini_uart::MiniUart::new(MINI_UART_BASE);
|
||||
mini_uart.init(&gpio);
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Configure JTAG pins
|
||||
//------------------------------------------------------------
|
||||
setup_jtag(&gpio);
|
||||
|
||||
mini_uart.puts("\n[i] JTAG is live. Please connect.\n");
|
||||
|
||||
loop {}
|
||||
}
|
||||
|
||||
raspi3_boot::entry!(kernel_entry);
|
||||
@ -0,0 +1,218 @@
|
||||
/*
|
||||
* MIT License
|
||||
*
|
||||
* Copyright (c) 2018-2019 Andre Richter <andre.o.richter@gmail.com>
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*/
|
||||
|
||||
use super::gpio;
|
||||
use core::ops;
|
||||
use cortex_a::asm;
|
||||
use register::{mmio::*, register_bitfields};
|
||||
|
||||
/// Auxilary mini UART registers
|
||||
//
|
||||
// Descriptions taken from
|
||||
// https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
|
||||
register_bitfields! {
|
||||
u32,
|
||||
|
||||
/// Auxiliary enables
|
||||
AUX_ENABLES [
|
||||
/// If set the mini UART is enabled. The UART will immediately
|
||||
/// start receiving data, especially if the UART1_RX line is
|
||||
/// low.
|
||||
/// If clear the mini UART is disabled. That also disables any
|
||||
/// mini UART register access
|
||||
MINI_UART_ENABLE OFFSET(0) NUMBITS(1) []
|
||||
],
|
||||
|
||||
/// Mini Uart Interrupt Identify
|
||||
AUX_MU_IIR [
|
||||
/// Writing with bit 1 set will clear the receive FIFO
|
||||
/// Writing with bit 2 set will clear the transmit FIFO
|
||||
FIFO_CLEAR OFFSET(1) NUMBITS(2) [
|
||||
Rx = 0b01,
|
||||
Tx = 0b10,
|
||||
All = 0b11
|
||||
]
|
||||
],
|
||||
|
||||
/// Mini Uart Line Control
|
||||
AUX_MU_LCR [
|
||||
/// Mode the UART works in
|
||||
DATA_SIZE OFFSET(0) NUMBITS(2) [
|
||||
SevenBit = 0b00,
|
||||
EightBit = 0b11
|
||||
]
|
||||
],
|
||||
|
||||
/// Mini Uart Line Status
|
||||
AUX_MU_LSR [
|
||||
/// This bit is set if the transmit FIFO is empty and the transmitter is
|
||||
/// idle. (Finished shifting out the last bit).
|
||||
TX_IDLE OFFSET(6) NUMBITS(1) [],
|
||||
|
||||
/// This bit is set if the transmit FIFO can accept at least
|
||||
/// one byte.
|
||||
TX_EMPTY OFFSET(5) NUMBITS(1) [],
|
||||
|
||||
/// This bit is set if the receive FIFO holds at least 1
|
||||
/// symbol.
|
||||
DATA_READY OFFSET(0) NUMBITS(1) []
|
||||
],
|
||||
|
||||
/// Mini Uart Extra Control
|
||||
AUX_MU_CNTL [
|
||||
/// If this bit is set the mini UART transmitter is enabled.
|
||||
/// If this bit is clear the mini UART transmitter is disabled.
|
||||
TX_EN OFFSET(1) NUMBITS(1) [
|
||||
Disabled = 0,
|
||||
Enabled = 1
|
||||
],
|
||||
|
||||
/// If this bit is set the mini UART receiver is enabled.
|
||||
/// If this bit is clear the mini UART receiver is disabled.
|
||||
RX_EN OFFSET(0) NUMBITS(1) [
|
||||
Disabled = 0,
|
||||
Enabled = 1
|
||||
]
|
||||
],
|
||||
|
||||
/// Mini Uart Baudrate
|
||||
AUX_MU_BAUD [
|
||||
/// Mini UART baudrate counter
|
||||
RATE OFFSET(0) NUMBITS(16) []
|
||||
]
|
||||
}
|
||||
|
||||
#[allow(non_snake_case)]
|
||||
#[repr(C)]
|
||||
pub struct RegisterBlock {
|
||||
__reserved_0: u32, // 0x00
|
||||
AUX_ENABLES: ReadWrite<u32, AUX_ENABLES::Register>, // 0x04
|
||||
__reserved_1: [u32; 14], // 0x08
|
||||
AUX_MU_IO: ReadWrite<u32>, // 0x40 - Mini Uart I/O Data
|
||||
AUX_MU_IER: WriteOnly<u32>, // 0x44 - Mini Uart Interrupt Enable
|
||||
AUX_MU_IIR: WriteOnly<u32, AUX_MU_IIR::Register>, // 0x48
|
||||
AUX_MU_LCR: WriteOnly<u32, AUX_MU_LCR::Register>, // 0x4C
|
||||
AUX_MU_MCR: WriteOnly<u32>, // 0x50
|
||||
AUX_MU_LSR: ReadOnly<u32, AUX_MU_LSR::Register>, // 0x54
|
||||
__reserved_2: [u32; 2], // 0x58
|
||||
AUX_MU_CNTL: WriteOnly<u32, AUX_MU_CNTL::Register>, // 0x60
|
||||
__reserved_3: u32, // 0x64
|
||||
AUX_MU_BAUD: WriteOnly<u32, AUX_MU_BAUD::Register>, // 0x68
|
||||
}
|
||||
|
||||
pub struct MiniUart {
|
||||
base_addr: usize,
|
||||
}
|
||||
|
||||
/// Deref to RegisterBlock
|
||||
///
|
||||
/// Allows writing
|
||||
/// ```
|
||||
/// self.MU_IER.read()
|
||||
/// ```
|
||||
/// instead of something along the lines of
|
||||
/// ```
|
||||
/// unsafe { (*MiniUart::ptr()).MU_IER.read() }
|
||||
/// ```
|
||||
impl ops::Deref for MiniUart {
|
||||
type Target = RegisterBlock;
|
||||
|
||||
fn deref(&self) -> &Self::Target {
|
||||
unsafe { &*self.ptr() }
|
||||
}
|
||||
}
|
||||
|
||||
impl MiniUart {
|
||||
pub fn new(base_addr: usize) -> MiniUart {
|
||||
MiniUart { base_addr }
|
||||
}
|
||||
|
||||
/// Returns a pointer to the register block
|
||||
fn ptr(&self) -> *const RegisterBlock {
|
||||
self.base_addr as *const _
|
||||
}
|
||||
|
||||
///Set baud rate and characteristics (115200 8N1) and map to GPIO
|
||||
pub fn init(&self, gpio: &gpio::GPIO) {
|
||||
// initialize UART
|
||||
self.AUX_ENABLES.modify(AUX_ENABLES::MINI_UART_ENABLE::SET);
|
||||
self.AUX_MU_IER.set(0);
|
||||
self.AUX_MU_CNTL.set(0);
|
||||
self.AUX_MU_LCR.write(AUX_MU_LCR::DATA_SIZE::EightBit);
|
||||
self.AUX_MU_MCR.set(0);
|
||||
self.AUX_MU_IER.set(0);
|
||||
self.AUX_MU_IIR.write(AUX_MU_IIR::FIFO_CLEAR::All);
|
||||
self.AUX_MU_BAUD.write(AUX_MU_BAUD::RATE.val(270)); // 115200 baud
|
||||
|
||||
// map UART1 to GPIO pins
|
||||
gpio.GPFSEL1
|
||||
.modify(gpio::GPFSEL1::FSEL14::TXD1 + gpio::GPFSEL1::FSEL15::RXD1);
|
||||
|
||||
gpio.GPPUD.set(0); // enable pins 14 and 15
|
||||
for _ in 0..150 {
|
||||
asm::nop();
|
||||
}
|
||||
|
||||
gpio.GPPUDCLK0
|
||||
.write(gpio::GPPUDCLK0::PUDCLK14::AssertClock + gpio::GPPUDCLK0::PUDCLK15::AssertClock);
|
||||
for _ in 0..150 {
|
||||
asm::nop();
|
||||
}
|
||||
|
||||
gpio.GPPUDCLK0.set(0);
|
||||
|
||||
self.AUX_MU_CNTL
|
||||
.write(AUX_MU_CNTL::RX_EN::Enabled + AUX_MU_CNTL::TX_EN::Enabled);
|
||||
|
||||
// Clear FIFOs before using the device
|
||||
self.AUX_MU_IIR.write(AUX_MU_IIR::FIFO_CLEAR::All);
|
||||
}
|
||||
|
||||
/// Send a character
|
||||
fn putc(&self, c: char) {
|
||||
// wait until we can send
|
||||
loop {
|
||||
if self.AUX_MU_LSR.is_set(AUX_MU_LSR::TX_EMPTY) {
|
||||
break;
|
||||
}
|
||||
|
||||
asm::nop();
|
||||
}
|
||||
|
||||
// write the character to the buffer
|
||||
self.AUX_MU_IO.set(c as u32);
|
||||
}
|
||||
|
||||
/// Display a string
|
||||
pub fn puts(&self, string: &str) {
|
||||
for c in string.chars() {
|
||||
// convert newline to carrige return + newline
|
||||
if c == '\n' {
|
||||
self.putc('\r')
|
||||
}
|
||||
|
||||
self.putc(c);
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue