From 68de789d15555514aa92bf83f3f53a3b43fbf34f Mon Sep 17 00:00:00 2001
From: Andre Richter <andre.o.richter@gmail.com>
Date: Tue, 2 Oct 2018 22:59:27 +0200
Subject: [PATCH] 0D: Instruction caching and better benchmark function.

The previous benchmark function had a few flaws. First of all, it wasn't
idiomatic Rust, because we used a loop construct that you would expect in C.
Revamped that by using an iterator. Also, the previous benchmark got heavily
optimized by the compiler, which unrolled the inner loop it into a huge sequence
of consecutive loads and stores, resulting in lots of instructions that needed
to be fetched from DRAM. Additionally, instruction caching was not turned on.

The new code compiles into two tight loops, fully leveraging the power of the I
and D caches, and providing an great showcase.
---
 0C_virtual_memory/kernel8             | Bin 73056 -> 73056 bytes
 0C_virtual_memory/kernel8.img         | Bin 2572 -> 2572 bytes
 0C_virtual_memory/src/mmu.rs          |   4 ++--
 0D_cache_performance/README.md        |  10 +++++-----
 0D_cache_performance/kernel8          | Bin 79448 -> 79496 bytes
 0D_cache_performance/kernel8.img      | Bin 6912 -> 6016 bytes
 0D_cache_performance/src/benchmark.rs |  21 ++++++++++-----------
 0D_cache_performance/src/mmu.rs       |   4 ++--
 8 files changed, 19 insertions(+), 20 deletions(-)

diff --git a/0C_virtual_memory/kernel8 b/0C_virtual_memory/kernel8
index 5fab5fd377f738ebfc4fd9004d40dee6b64494ea..727ac4099686cd6c01d27ee380b2e1aa883bff88 100755
GIT binary patch
delta 202
zcmaE`i{-&CmWC~iMU0G1+lv_)Q~4P?w%-(B{LaXzJpG~&qc~&W_LoA8>lr0au`n<Q
zF)%XR;NV~Y0SL*!&@g?Y2&1@UD=S1ACZPdV#K16d`a_VkAsYjO00T1vg8@t*MBaM4
zpeW-G77;@e14DBYBV%)OV-quD15-0IOT+1RBpLOv%50aFVm!#W{ed)N0wbgQbVpf6
Fc>tBTCm{d;

delta 200
zcmaE`i{-&CmWC~iMU0FM+lv_)Q~4R&x8D?C{LaXzIQ^m!qd24g_LoA8>lr0aurM$P
zF)%XR;NV~Y0SL*!P&a*}2&1@UGb=<ICZPdV#K6!${UJzNpN)Y*fPtBT!2qTYB5%1}
zP?T{8i?FGQrKzE@iK&^ffvJ(Pxsj2H<@CFfjC$B4w#!Q~9%S5pPnt1_k<oR!qb#F5
E079T9tpET3

diff --git a/0C_virtual_memory/kernel8.img b/0C_virtual_memory/kernel8.img
index d82eb38d00af783af65562896abbd59e69392a12..cf0dcb19399c49299f4a458b67f2de17cf4a9771 100755
GIT binary patch
delta 14
VcmeAX=@Hpb#K_pRxtMV#2LL3i1g`)9

delta 14
VcmeAX=@Hpb#K_pNxtMV#2LL3W1g!u7

diff --git a/0C_virtual_memory/src/mmu.rs b/0C_virtual_memory/src/mmu.rs
index c2bf1500..13048dad 100644
--- a/0C_virtual_memory/src/mmu.rs
+++ b/0C_virtual_memory/src/mmu.rs
@@ -219,8 +219,8 @@ pub unsafe fn init() {
     // First, force all previous changes to be seen before the MMU is enabled.
     barrier::isb(barrier::SY);
 
-    // Enable the MMU and turn on caching
-    SCTLR_EL1.modify(SCTLR_EL1::M::Enable + SCTLR_EL1::C::Cacheable);
+    // Enable the MMU and turn on data and instruction caching.
+    SCTLR_EL1.modify(SCTLR_EL1::M::Enable + SCTLR_EL1::C::Cacheable + SCTLR_EL1::I::Cacheable);
 
     // Force MMU init to complete before next instruction
     barrier::isb(barrier::SY);
diff --git a/0D_cache_performance/README.md b/0D_cache_performance/README.md
index 1f1dee0a..bfaa50b7 100644
--- a/0D_cache_performance/README.md
+++ b/0D_cache_performance/README.md
@@ -13,7 +13,7 @@ performance.
 ## Benchmark
 
 Let's write a tiny, arbitrary micro-benchmark to showcase the performance of
-operating on the same DRAM with caching enabled and disabled.
+operating with data on the same DRAM with caching enabled and disabled.
 
 ### mmu.rs
 
@@ -31,7 +31,7 @@ block). This time, the block is configured as cacheable.
 We write a little function that iteratively reads memory of five times the size
 of a `cacheline`, in steps of 8 bytes, aka one processor register at a time. We
 read the value, add 1, and write it back. This whole process is repeated
-`100_000` times.
+`20_000` times.
 
 ### main.rs
 
@@ -46,12 +46,12 @@ On my Raspberry, I get the following results:
 
 ```text
 Benchmarking non-cacheable DRAM modifications at virtual 0x00200000, physical 0x00400000:
-664 miliseconds.
+1040 miliseconds.
 
 Benchmarking cacheable DRAM modifications at virtual 0x00400000, physical 0x00400000:
-148 miliseconds.
+53 miliseconds.
 
-With caching, the function is 348% faster!
+With caching, the function is 1862% faster!
 ```
 
 Impressive, isn't it?
diff --git a/0D_cache_performance/kernel8 b/0D_cache_performance/kernel8
index 7c8f3aedef6c3d1cd33ebf8c75b657890fe450ea..8b80d88b063b31515cef721fbfba10f67ba0720c 100755
GIT binary patch
delta 2965
zcmZXWeQZ-z6u{4U?bfbi?sY3|H#gRe3SCEVD;*mevoR7tA_)vaL`l{eH47|CAcmL#
zuPC5=MPEd3)Wi*A3<8EOQR<YKk)X~H2r5MUN4r79WhfF1AI4bEd-q(jK5x>U-QPL)
zeB68PZ7*GOzxuoT^%#ztjcvYk2<(v#4Xr<s*M4$;+JGw%UlN-U*BU1Q4yFK-JrUQ%
zd_Et#InX(*0R-x3-dEi@9PqnW?bG1kfCd|S^ZC^XkTJB*;rfwEvr9{N=Qe9*pmRre
zz&*Ihg>cZ)*Lwq|#m7ChiGRue_IzI0yf0uj@R~csi5Z#tbh-JIM>@Jm&{{a=Dow0a
z&iZxpeU$pidwO4DrP2@TGMK9_ahdcJuDT<!+`|`rr}uPElAnI;yt}^$%>G?)XFw~R
z+(AV&(!2wGlbAR1s|Pw<7vr>`ggz5xkX(x1Grn!<?g>{(+`G;9u9Z+_$+z!}xhmu5
zRM5j5v>Xy&%Stl!S9Ei{SSEUEN}{vXnkj`0EB$hpFHxrqrc^RCrINkcQnQq*xkk1J
zsG5%{`vX)>4^Ep>O(|6)W_hq3b<yL&nOG@a_TX$1M?GlN1kKA7CIXQQ)C?I&SD3%>
zJekif_Tu9n42XepT!KMywH)U+>{wvt76BcF_sGOi_eVZjHSr+aEg{+18#b4Xg++&s
zQ9a{56f}P;uf1bgEISkwn{`}=8F6068CWf@>$uaM**{h-w)ipW&TOFnj{C93n|T0z
zXS#CL*&qD4zDQeGCOSe`Z=TgfDug2y>44Yn+A8}mz{Y?`gmJevXS(=2jEfhgrWfj0
z@LXs6StN_-6P+gQ7z6d3J^JtSnx|?-stVgHa=bReItXTuRN-^QL+8^j5sqLAd&P?p
z?7=g_j9>`IrMPPgL$_UOFv=O<bHe;r2d`oNr-L^z*Ek#HC&s+m!RJbDK(4Z|#Cg2n
zen)_I<}n9<gn8V-yO=L<@FmPQ+I)`66W}pcsIyZVx~eoZ7^E|7z*)U(>^Z_G?!v^M
zB(Bj3?L^6&UDCrI;z$}95TKMDzs6j}Q@!%0xG@t$hRSn}W8+ks?GCQeI_XI37^fR8
zE=+fb`KYImpOD;uW?!K~)u9qnbwrD)ZVm6*U$Y$mbTd~0`siV{Mw+=ww2$qNGna|Z
z1o(gzJs#RXO#@YNSo(o4?2W?jrI?W0MjK5-19hX=7P#L)-8{uryQLl5sj5|e)Xh|<
zru?W=`<b$*Br8BUigAP@F&3p;S7VE+hwStaY8)54!&V!sIs3zoY@T4AbMO>%2o|2z
zv&_Q|-p{<<!R3~s@xKR$y8&X3d^g#S5H>pa7Ut(2d@FJ5a;OK*&AW4qxEpTd<y8C;
zMV~QZ`_SMsN0Q&L@6>&T#hzpCE-U2QX=?S2)6a;5k8&;-WG>=r6#b$(f?ogAj!4(-
zQ)*G0La#6{l|rMh7waY{9$>9otej0PP$k7&DY~RsBgF<=JZji)21455c^C74{Dl$s
z5x2Hgaq9<;HO8gaTT=MM!WhM$Aw@!pRZ_el#amKjrMM)%i(#Fy!tpe#CuXOEtEL7h
z%<d+gvi%~meW#rpz<l~@v$*n~WWJZUP8x{Ve#G;QSYo_kL#wVr=kF1(ASdc3DeZ0M
zs$-Y3^E!G(EPM5AEBh#O)yXNgACz3&ZbZLvjEz)7sKsA0SFN{>_rI15tYE5DRl6^z
z4zaj8->vq!0_<k4u8rD}EO8xN;*~i1@l^KhIF_N-(jt1BFqr+Y37d*5THD&1lk?gV
zZLQ5M$z-x6IX`=)1^?2-k4dc8PFIS*lQ`F>zGZWjBGHPw%SP$<jy34jf@j26t=NR4
W;zlcW_;1B!4QDB|J;YEIhW-QnA+iAg

delta 3856
zcmZXW4{Te-9mntY>^P2_q=}u_`O~J335nxQp>-0s4O=lO%F+l$5TXtu)}~PvD#OA^
zrB3T;UlyT=RjkUZLJopN!$4Y{Rcb-dw1`PTLO@%j4XNFxO#-Lgv{tmJWo04~!u!5=
zzeDxgldSvP_xHQs{odX0?)mu}-oIV<PRHpbt94UA)C=|0znM9mH~v`kPK+KRnvna5
z9y8}j%nS?Bu`BAil+WiQw~wXI8bVa9L;v}@^x06Q_mQVPV#YMYle_czK@#HBF(ZAp
zajDVjHYNsg`wS~Y69ZKjrw2mb`SA`hKmISowEY_WG0V1JE?%3=L3=izmyW(SX2sN4
z)B3x1o>*&*6sv%jpxFbLJ*$#m<JV<yz^59l-(fP__R04?fn-wK=Nr_7o^{C&V87<6
zT8QWFy|iGYS6Yk2t-c~*Ef``YgTBof!$il&9UnNr8~~RymxF`ML2#Hk46b9Y12-@?
zfMd)ta5Hl=IKi9%w}DMNi#BwUY)FDr%qegea~F6k^Hy*-b2qq$xd+_G+z0Mw?gtMr
z4}f<t?+`0yW{5jOFzjUB2_9h{0gp0|f-}q+@EG$Lc$|40yq|eL_yF?(@FC_y;7Nx~
zD>I4C6dR_%hnWw9k1!trA7wrYo@Jf|&oR%5mF1iH!DIJ%E+w$%CH8NP=;$T?g}}jy
zfoq<Ug#TdR6}xt-QA5@K`SDPRd2Vjm6H5F@7tnDopw%MTsSER;4c29!D!L7K6y1M4
zf#i$Y=Z?Z`xx?qT+I~l2u7hS5<vAn0GGqG0EmWp;&JZhE2sUSJ_A&dw0p<X>oVgqv
zWDbJE%wcdHa~&8(>BK})W@F4TaI<1F+l)?v4GC}?a~n9xoCK$sQ{XP<E-;GHnE*wZ
z?Pl%<_b~T>`<VN{{mlK~fwZXx51_My4LiU?%tK%lr85DFGCRUN0v=@^1!tHu;4$Vg
zFpAO{I}YB@ydQjk`M@4@P?e4osxmvtJPDp+o&q0cJ`6s>d<2Z5bjBV9&oa+~=a`+M
zl(Qb%Obzl+9=eMf<$pZXf~MX}=9(t!3d$iWq8D*TpAr*M>vQfu^xfiVFFjgJF}b>w
zeoRgBC#95%y<cqQwh7#f{)KCQ@MZ%-OkcZ4tdyW_-Q8^UEjP=PrPNe0?SHMwy1IJp
zH?~LLYfbV>DLqcpGF?Uu6qmco=sEB73(Il&?=tG}PCp4+S59mE(|1$gLU%5{xUHNr
zMaHk|<;f6|&4p+wC~Ex9m!wvGPsGiLe5;D4j1x7otD1VY<y`hZbH9T9ThJEa_x5TP
zhh>3pg7bV^>9^irD|6MfIXGOae4=cds9j8iY0M{UqBKm~<u9YOi_S|cN)cLi8uJ^+
z)eyZrEsqr6u|De3z0SOb__<3Dus-S1D_Ea%>0zatVmMOxUiCcS6_*}m{kTiNoAm{k
zo?!i~OTUNpn~wei{l55`vq5i|wrpWNS|j^n)VzDE(<kwOzcBG_&<$+MbENbopNjAd
zbb>`qD8wob{0r9ge7Zmm%1>hyF?F6NTnneuJmb=JS`WI?vj0@r3A|lWnC{E0Kf0<=
ze^u$GSSl+t==abG>Gvqbdm09P?|<D1AVe4IdV;<9hh#r{S=Wi~Wq--KO7t!v-e5y-
zG4eMIq2IVh#SyPN3q|j$=2Nw7SDitI(8q{<1=pL<$4%?H+yoyTt?RedarAN2yQbsl
zUHcH(Bgvr9f#MwLhDy&XmzyY38*>(c#0l4FZgI@!4;`~1;;wAES=R?#XW7g8gv-C5
z^_N`wAnRvbx>`~)|L>OJY7l2!`3^aOu+|lYMY4<aVVAxKx_vnGE#~Dnn1SvUxALkh
zzigs_dEAL%h|P6{u}^aBo0Wz7Y1U_4b3Oq#yKdZZvM&8&&gDIoi~OjWYAbKMCi$zg
zK^ygY;MUc9;Iv<$YaarwSF!cFGmJ<++=4qdteS*swyNe4r`i65#~wnWB3KytXRN<a
zU8wJaZm+1;2l=#|S5ZGx%~z`N$@}A&zfLvxs^+JvIi#9ns#$Uxxgkpa)?B!7N`1vt
zxvtch+}KKy?f<~0+8Jqcn%AHKpD$b2;W}6!hh71Th!#%sD`_E|IR$eN!}L+nPM@=`
zOR|^4`EgCy{`y|l{$;G|QXOXh-)LPZ&p7KZD%}*i1azR^^8j6EkMoNA;9yUz>r&Tt
z3jZ%`UGM0#&Q1#PH0%0|==GR~ULoL=wrAAWD{x`)%><Rv;$PO&dS7VcrY)Pcw0CZ5
zPjx0!8<L&v?d^-9B;7WozmuZIU_>T5sV$(ttHTjF(n(Wgr|_S~esE8TJ@V^LT2H5B
WV~Xyp{7ii+#c9m%JaS{0BL4$Pln?O$

diff --git a/0D_cache_performance/kernel8.img b/0D_cache_performance/kernel8.img
index ec0a16b0869abc221cdd3eaa4386dc7c504a0dd8..d68c9481518e50b021f1db6216a1b09ea652038c 100755
GIT binary patch
delta 794
zcmY*XOK1~O6uoa|>P#lBnKaWR4XycDTU&&}5Q^d=F+wc`p~g}y2yI;zn}wK#tD31l
zP+Rcv0)j5my3!VLN>&jU3L;2F1kJ*gNh@fG;G&y$<9H`CkvQ-^_ndp~y@xmYh(7!v
z!hIDsV-tkjU|BMqdj*i61&Gf?__Ar5f!#u~!~v*bjORnilIj)C-{&A-;9z0SG$#pw
zk>ir3=xZNMaeBIv<*1rmN~^-^Rh~fJ;-ivEEqq(-)&5}p>!$gzfzPWn=4kd1M=WPV
zbq~EH+J$xzw1idOtxY$JWfb~^*nIsTFKg$T{HkI%<HOnx@-;rZezbD3EWf>*u4A1H
zN$xMV0nOZoy#nX1FQJJ+j1xqz6EkN{77~1U2n8-&wGN1n5ot?a)YCQIH6$&{kF9}x
zuJ@0syl?1Zv*}Z(sRy)owi6@zU7_0t>_OkO3_8%%v=}Kh`Ln#Ng_{X2PBvSd+~dZm
z8{PcE+!b{59H(DFH#4NY#f=-?uzvA4QP_-lnE2RDaRB!XG1ud#JJ=!ukuQL+19~U@
z=EQNcI4WHbiOLF|GsMq+ct&DNCurp~;2TKmwGH8!jFQ?g?7Q$BoD0(NYLF$AKE;sM
z{Pd@%ch5=~U-Pr9a*-J9lX8fJ*l*>QU@TWd?3y<&7z=oL;q8%(BShXxRYJwj-pg&=
zsScJ1L<JlP*ks^Cr>;uY9l9Gkz!jBg!8_csF7`4wnwstUpPg`G#mVl+vkg~YyPfC2
afd5$I%N%5>?y1g-Ba1jN_>1e^Q{*qhgz&-u

delta 1708
zcmZA2ZD<>H90&0K-6d&yw&|9%*_yR!a@MrVi%yOjB;pJiM9GUX;)q&g4?&7#QXzxB
zC~g;v1Swi_y&9puXyz+Zh3P6nUkFq7rfi@u);GQ}*%a-&4IeNd#_wIekz(L-pWpxY
ze>ljOOZikeQH{u7yT8!RN>bUnBE4eNC9!c)h}jDfWxvzu9Q%DMwJQrTJc0V%P--`D
z)b-+<ir6q@arsiGb50WC^DQ~G8@&}Z({ef2yds+cshk_WSIq@n_0p`Umwv{c_PnT9
zGwuHUzHz;Yv9~&%51sMXHB;-ZHOwD+lgr~~p|88)KE~{YE#)!&4_rx^8@>@XKgMBp
z@9uwdR9)}&>*4N!%7lI!{R3rqd%F3|{<fTIpLB~yS+_8^WzjC8wq2AB6do2HSfy3i
zNBdwu?T3SO5Dw8HI829Ojn?289fRX^9G-y<`zdBn=xpe4f=<9mItibqPs3?C4QJ>K
zoTany96bl;=p3A<^P+7O=UL37ah^U87w7`KKrg^Wx(F}Qi*Si9!AtZKyi6~{*XV2T
zietkpuAr!}QGr+KRd|hFgV*VGxJK9DO?p$bTMs+uww_b=<M_?{?Q2ZTz94z;s8`Fm
z1EoLiy{dj>XJ-T%8u8Xkfqr9ev!w*$&-McJ2?I1F^rw2k{3&eS_jE(|<e||0si^t~
zy*Y=1Idy2x`@R05U`}An4&|PlYHt`G@d(K@_hiv-V8C|6wukn>Dy_mk+6Vh-KOCfk
zaEK1U2&J<pLfO!04UTnfG-4>?Y{cOidIr{M9Zt{*I7ugAgwi<xp=_k-G@PL`aF))(
zbMzdXOBvn8ITU#|^6)%84<nS$0SINIKo{TzdI2udMR<{3gb_+-Z3$kYm*8c3`85<s
zr85bsY^=~LaD}eGtMn?oMz6sLrL%S&uF*AklXgOB)s&~Du=SntxD>U1Q>O5J!exw2
znhy|#h=|-1cv*^a#Qc%<*?)Gva=qLqY1Yud^U|dC(m+D{rq67i5qKqfw+}vbHB=$0
z2d6~4ANP}&VrI4#vu+Gb9;te-Pny3DjsIm&$X=hc9t^xHRjt%uSemvj48G&4zSo+z
zei@u~RWAb*zA<n02}!+^Zcgu<@fF?j+b66WfvD9C-13X#UObr)qt3Sw506<lhb!`D
z$F1Z@Cf)pB_j}eyIC~0rH?A*-y1Q^#;2*&G{C(8=b|mk=INEJTI9wjxi3ju2zfzo7
AA^-pY

diff --git a/0D_cache_performance/src/benchmark.rs b/0D_cache_performance/src/benchmark.rs
index e4f7ce1d..ad01dc91 100644
--- a/0D_cache_performance/src/benchmark.rs
+++ b/0D_cache_performance/src/benchmark.rs
@@ -3,26 +3,25 @@ use cortex_a::{barrier, regs::*};
 
 /// We assume that addr is cacheline aligned
 pub fn batch_modify(addr: u64) -> u32 {
-    const CACHELINE_SIZE_BYTES: u64 = 64; // TODO: retrieve this from a system register
-    const NUM_CACHELINES_TOUCHED: u64 = 5;
-    const BYTES_PER_U64_REG: usize = 8;
-    const NUM_BENCH_ITERATIONS: u64 = 100_000;
+    const CACHELINE_SIZE_BYTES: usize = 64; // TODO: retrieve this from a system register
+    const NUM_CACHELINES_TOUCHED: usize = 5;
+    const NUM_BENCH_ITERATIONS: usize = 20_000;
 
-    const NUM_BYTES_TOUCHED: u64 = CACHELINE_SIZE_BYTES * NUM_CACHELINES_TOUCHED;
+    const NUM_BYTES_TOUCHED: usize = CACHELINE_SIZE_BYTES * NUM_CACHELINES_TOUCHED;
 
+    let mem = unsafe { core::slice::from_raw_parts_mut(addr as *mut u64, NUM_BYTES_TOUCHED) };
+
+    // Benchmark starts here
     let t1 = CNTPCT_EL0.get();
 
     compiler_fence(Ordering::SeqCst);
 
-    let mut data_ptr: *mut u64;
     let mut temp: u64;
     for _ in 0..NUM_BENCH_ITERATIONS {
-        for i in (addr..(addr + NUM_BYTES_TOUCHED)).step_by(BYTES_PER_U64_REG) {
-            data_ptr = i as *mut u64;
-
+        for qword in mem.iter_mut() {
             unsafe {
-                temp =  core::ptr::read_volatile(data_ptr);
-                core::ptr::write_volatile(data_ptr, temp + 1);
+                temp = core::ptr::read_volatile(qword);
+                core::ptr::write_volatile(qword, temp + 1);
             }
         }
     }
diff --git a/0D_cache_performance/src/mmu.rs b/0D_cache_performance/src/mmu.rs
index a379c769..df48d434 100644
--- a/0D_cache_performance/src/mmu.rs
+++ b/0D_cache_performance/src/mmu.rs
@@ -211,8 +211,8 @@ pub unsafe fn init() {
     // First, force all previous changes to be seen before the MMU is enabled.
     barrier::isb(barrier::SY);
 
-    // Enable the MMU and turn on caching
-    SCTLR_EL1.modify(SCTLR_EL1::M::Enable + SCTLR_EL1::C::Cacheable);
+    // Enable the MMU and turn on data and instruction caching.
+    SCTLR_EL1.modify(SCTLR_EL1::M::Enable + SCTLR_EL1::C::Cacheable + SCTLR_EL1::I::Cacheable);
 
     // Force MMU init to complete before next instruction
     barrier::isb(barrier::SY);