From 163e2010ab2044a8194bdaf7a59204a8a0bbaa68 Mon Sep 17 00:00:00 2001
From: Andre Richter <andre.o.richter@gmail.com>
Date: Sat, 14 Nov 2020 09:57:31 +0100
Subject: [PATCH] GPIO: Fix RPi4 driver init

The RPi4 GPIO pull-up/pull down sequence is done differently than on the
RPi3. Switch to using the correct way.

Also, configure pull-ups for both UART pins.

Fixes #81
---
 06_drivers_gpio_uart/README.md                | 110 ++++++++++++++----
 06_drivers_gpio_uart/src/_arch/aarch64/cpu.rs |   1 +
 .../src/bsp/device_driver/bcm/bcm2xxx_gpio.rs | 105 +++++++++++++----
 07_uart_chainloader/README.md                 |   2 +-
 07_uart_chainloader/demo_payload_rpi3.img     | Bin 6896 -> 7384 bytes
 07_uart_chainloader/demo_payload_rpi4.img     | Bin 6880 -> 7240 bytes
 07_uart_chainloader/src/_arch/aarch64/cpu.rs  |   1 +
 .../src/bsp/device_driver/bcm/bcm2xxx_gpio.rs | 105 +++++++++++++----
 08_timestamps/README.md                       |  54 ++++++++-
 08_timestamps/src/_arch/aarch64/cpu.rs        |   8 --
 .../src/bsp/device_driver/bcm/bcm2xxx_gpio.rs |  99 ++++++++++++----
 09_hw_debug_JTAG/src/_arch/aarch64/cpu.rs     |   8 --
 .../src/bsp/device_driver/bcm/bcm2xxx_gpio.rs |  99 ++++++++++++----
 10_privilege_level/src/_arch/aarch64/cpu.rs   |   8 --
 .../src/bsp/device_driver/bcm/bcm2xxx_gpio.rs |  99 ++++++++++++----
 .../src/_arch/aarch64/cpu.rs                  |   8 --
 .../src/bsp/device_driver/bcm/bcm2xxx_gpio.rs |  99 ++++++++++++----
 .../src/_arch/aarch64/cpu.rs                  |   8 --
 .../src/bsp/device_driver/bcm/bcm2xxx_gpio.rs |  99 ++++++++++++----
 13_integrated_testing/README.md               |   2 +-
 .../src/_arch/aarch64/cpu.rs                  |   8 --
 .../src/bsp/device_driver/bcm/bcm2xxx_gpio.rs |  99 ++++++++++++----
 14_exceptions_part2_peripheral_IRQs/README.md |   6 +-
 .../src/_arch/aarch64/cpu.rs                  |   8 --
 .../src/bsp/device_driver/bcm/bcm2xxx_gpio.rs |  99 ++++++++++++----
 15_virtual_mem_part2_mmio_remap/README.md     |  18 +--
 .../src/_arch/aarch64/cpu.rs                  |   8 --
 .../src/bsp/device_driver/bcm/bcm2xxx_gpio.rs |  99 ++++++++++++----
 X1_JTAG_boot/jtag_boot_rpi3.img               | Bin 7512 -> 8992 bytes
 X1_JTAG_boot/jtag_boot_rpi4.img               | Bin 7496 -> 7384 bytes
 X1_JTAG_boot/src/_arch/aarch64/cpu.rs         |  10 +-
 .../src/bsp/device_driver/bcm/bcm2xxx_gpio.rs |  99 ++++++++++++----
 32 files changed, 1015 insertions(+), 354 deletions(-)

diff --git a/06_drivers_gpio_uart/README.md b/06_drivers_gpio_uart/README.md
index e89ef1c6..ec28b067 100644
--- a/06_drivers_gpio_uart/README.md
+++ b/06_drivers_gpio_uart/README.md
@@ -183,13 +183,14 @@ diff -uNr 05_safe_globals/Makefile 06_drivers_gpio_uart/Makefile
 diff -uNr 05_safe_globals/src/_arch/aarch64/cpu.rs 06_drivers_gpio_uart/src/_arch/aarch64/cpu.rs
 --- 05_safe_globals/src/_arch/aarch64/cpu.rs
 +++ 06_drivers_gpio_uart/src/_arch/aarch64/cpu.rs
-@@ -37,6 +37,16 @@
+@@ -37,6 +37,17 @@
  // Public Code
  //--------------------------------------------------------------------------------------------------
 
 +pub use asm::nop;
 +
 +/// Spin for `n` cycles.
++#[cfg(feature = "bsp_rpi3")]
 +#[inline(always)]
 +pub fn spin_for_cycles(n: usize) {
 +    for _ in 0..n {
@@ -204,7 +205,7 @@ diff -uNr 05_safe_globals/src/_arch/aarch64/cpu.rs 06_drivers_gpio_uart/src/_arc
 diff -uNr 05_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 06_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
 --- 05_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
 +++ 06_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
-@@ -0,0 +1,161 @@
+@@ -0,0 +1,222 @@
 +// SPDX-License-Identifier: MIT OR Apache-2.0
 +//
 +// Copyright (c) 2018-2020 Andre Richter <andre.o.richter@gmail.com>
@@ -212,7 +213,7 @@ diff -uNr 05_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 06_drivers_g
 +//! GPIO Driver.
 +
 +use crate::{
-+    bsp::device_driver::common::MMIODerefWrapper, cpu, driver, synchronization,
++    bsp::device_driver::common::MMIODerefWrapper, driver, synchronization,
 +    synchronization::NullLock,
 +};
 +use register::{mmio::*, register_bitfields, register_structs};
@@ -224,7 +225,8 @@ diff -uNr 05_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 06_drivers_g
 +// GPIO registers.
 +//
 +// Descriptions taken from
-+// https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
++// - https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
++// - https://datasheets.raspberrypi.org/bcm2711/bcm2711-peripherals.pdf
 +register_bitfields! {
 +    u32,
 +
@@ -246,7 +248,21 @@ diff -uNr 05_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 06_drivers_g
 +        ]
 +    ],
 +
++    /// GPIO Pull-up/down Register
++    ///
++    /// BCM2837 only.
++    GPPUD [
++        /// Controls the actuation of the internal pull-up/down control line to ALL the GPIO pins.
++        PUD OFFSET(0) NUMBITS(2) [
++            Off = 0b00,
++            PullDown = 0b01,
++            PullUp = 0b10
++        ]
++    ],
++
 +    /// GPIO Pull-up/down Clock Register 0
++    ///
++    /// BCM2837 only.
 +    GPPUDCLK0 [
 +        /// Pin 15
 +        PUDCLK15 OFFSET(15) NUMBITS(1) [
@@ -259,23 +275,37 @@ diff -uNr 05_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 06_drivers_g
 +            NoEffect = 0,
 +            AssertClock = 1
 +        ]
++    ],
++
++    /// GPIO Pull-up / Pull-down Register 0
++    ///
++    /// BCM2711 only.
++    GPIO_PUP_PDN_CNTRL_REG0 [
++        /// Pin 15
++        GPIO_PUP_PDN_CNTRL15 OFFSET(30) NUMBITS(2) [
++            NoResistor = 0b00,
++            PullUp = 0b01
++        ],
++
++        /// Pin 14
++        GPIO_PUP_PDN_CNTRL14 OFFSET(28) NUMBITS(2) [
++            NoResistor = 0b00,
++            PullUp = 0b01
++        ]
 +    ]
 +}
 +
 +register_structs! {
 +    #[allow(non_snake_case)]
 +    RegisterBlock {
-+        (0x00 => GPFSEL0: ReadWrite<u32>),
++        (0x00 => _reserved1),
 +        (0x04 => GPFSEL1: ReadWrite<u32, GPFSEL1::Register>),
-+        (0x08 => GPFSEL2: ReadWrite<u32>),
-+        (0x0C => GPFSEL3: ReadWrite<u32>),
-+        (0x10 => GPFSEL4: ReadWrite<u32>),
-+        (0x14 => GPFSEL5: ReadWrite<u32>),
-+        (0x18 => _reserved1),
-+        (0x94 => GPPUD: ReadWrite<u32>),
++        (0x08 => _reserved2),
++        (0x94 => GPPUD: ReadWrite<u32, GPPUD::Register>),
 +        (0x98 => GPPUDCLK0: ReadWrite<u32, GPPUDCLK0::Register>),
-+        (0x9C => GPPUDCLK1: ReadWrite<u32>),
-+        (0xA0 => @END),
++        (0x9C => _reserved3),
++        (0xE4 => GPIO_PUP_PDN_CNTRL_REG0: ReadWrite<u32, GPIO_PUP_PDN_CNTRL_REG0::Register>),
++        (0xE8 => @END),
 +    }
 +}
 +
@@ -314,26 +344,58 @@ diff -uNr 05_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 06_drivers_g
 +        }
 +    }
 +
++    /// Disable pull-up/down on pins 14 and 15.
++    #[cfg(feature = "bsp_rpi3")]
++    fn disable_pud_14_15_bcm2837(&mut self) {
++        use crate::cpu;
++
++        // Make an educated guess for a good delay value (Sequence described in the BCM2837
++        // peripherals PDF).
++        //
++        // - According to Wikipedia, the fastest Pi3 clocks around 1.4 GHz.
++        // - The Linux 2837 GPIO driver waits 1 µs between the steps.
++        //
++        // So lets try to be on the safe side and default to 2000 cycles, which would equal 1 µs
++        // would the CPU be clocked at 2 GHz.
++        const DELAY: usize = 2000;
++
++        self.registers.GPPUD.write(GPPUD::PUD::Off);
++        cpu::spin_for_cycles(DELAY);
++
++        self.registers
++            .GPPUDCLK0
++            .write(GPPUDCLK0::PUDCLK15::AssertClock + GPPUDCLK0::PUDCLK14::AssertClock);
++        cpu::spin_for_cycles(DELAY);
++
++        self.registers.GPPUD.write(GPPUD::PUD::Off);
++        self.registers.GPPUDCLK0.set(0);
++    }
++
++    /// Disable pull-up/down on pins 14 and 15.
++    #[cfg(feature = "bsp_rpi4")]
++    fn disable_pud_14_15_bcm2711(&mut self) {
++        self.registers.GPIO_PUP_PDN_CNTRL_REG0.write(
++            GPIO_PUP_PDN_CNTRL_REG0::GPIO_PUP_PDN_CNTRL15::PullUp
++                + GPIO_PUP_PDN_CNTRL_REG0::GPIO_PUP_PDN_CNTRL14::PullUp,
++        );
++    }
++
 +    /// Map PL011 UART as standard output.
 +    ///
 +    /// TX to pin 14
 +    /// RX to pin 15
 +    pub fn map_pl011_uart(&mut self) {
-+        // Map to pins.
++        // Select the UART on pins 14 and 15.
 +        self.registers
 +            .GPFSEL1
-+            .modify(GPFSEL1::FSEL14::AltFunc0 + GPFSEL1::FSEL15::AltFunc0);
++            .modify(GPFSEL1::FSEL15::AltFunc0 + GPFSEL1::FSEL14::AltFunc0);
 +
-+        // Enable pins 14 and 15.
-+        self.registers.GPPUD.set(0);
-+        cpu::spin_for_cycles(150);
++        // Disable pull-up/down on pins 14 and 15.
++        #[cfg(feature = "bsp_rpi3")]
++        self.disable_pud_14_15_bcm2837();
 +
-+        self.registers
-+            .GPPUDCLK0
-+            .write(GPPUDCLK0::PUDCLK14::AssertClock + GPPUDCLK0::PUDCLK15::AssertClock);
-+        cpu::spin_for_cycles(150);
-+
-+        self.registers.GPPUDCLK0.set(0);
++        #[cfg(feature = "bsp_rpi4")]
++        self.disable_pud_14_15_bcm2711();
 +    }
 +}
 +
diff --git a/06_drivers_gpio_uart/src/_arch/aarch64/cpu.rs b/06_drivers_gpio_uart/src/_arch/aarch64/cpu.rs
index 9b2da60d..53f131f8 100644
--- a/06_drivers_gpio_uart/src/_arch/aarch64/cpu.rs
+++ b/06_drivers_gpio_uart/src/_arch/aarch64/cpu.rs
@@ -40,6 +40,7 @@ pub unsafe fn _start() -> ! {
 pub use asm::nop;
 
 /// Spin for `n` cycles.
+#[cfg(feature = "bsp_rpi3")]
 #[inline(always)]
 pub fn spin_for_cycles(n: usize) {
     for _ in 0..n {
diff --git a/06_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs b/06_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
index 0b01db4b..974ed70f 100644
--- a/06_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
+++ b/06_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
@@ -5,7 +5,7 @@
 //! GPIO Driver.
 
 use crate::{
-    bsp::device_driver::common::MMIODerefWrapper, cpu, driver, synchronization,
+    bsp::device_driver::common::MMIODerefWrapper, driver, synchronization,
     synchronization::NullLock,
 };
 use register::{mmio::*, register_bitfields, register_structs};
@@ -17,7 +17,8 @@ use register::{mmio::*, register_bitfields, register_structs};
 // GPIO registers.
 //
 // Descriptions taken from
-// https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
+// - https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
+// - https://datasheets.raspberrypi.org/bcm2711/bcm2711-peripherals.pdf
 register_bitfields! {
     u32,
 
@@ -39,7 +40,21 @@ register_bitfields! {
         ]
     ],
 
+    /// GPIO Pull-up/down Register
+    ///
+    /// BCM2837 only.
+    GPPUD [
+        /// Controls the actuation of the internal pull-up/down control line to ALL the GPIO pins.
+        PUD OFFSET(0) NUMBITS(2) [
+            Off = 0b00,
+            PullDown = 0b01,
+            PullUp = 0b10
+        ]
+    ],
+
     /// GPIO Pull-up/down Clock Register 0
+    ///
+    /// BCM2837 only.
     GPPUDCLK0 [
         /// Pin 15
         PUDCLK15 OFFSET(15) NUMBITS(1) [
@@ -52,23 +67,37 @@ register_bitfields! {
             NoEffect = 0,
             AssertClock = 1
         ]
+    ],
+
+    /// GPIO Pull-up / Pull-down Register 0
+    ///
+    /// BCM2711 only.
+    GPIO_PUP_PDN_CNTRL_REG0 [
+        /// Pin 15
+        GPIO_PUP_PDN_CNTRL15 OFFSET(30) NUMBITS(2) [
+            NoResistor = 0b00,
+            PullUp = 0b01
+        ],
+
+        /// Pin 14
+        GPIO_PUP_PDN_CNTRL14 OFFSET(28) NUMBITS(2) [
+            NoResistor = 0b00,
+            PullUp = 0b01
+        ]
     ]
 }
 
 register_structs! {
     #[allow(non_snake_case)]
     RegisterBlock {
-        (0x00 => GPFSEL0: ReadWrite<u32>),
+        (0x00 => _reserved1),
         (0x04 => GPFSEL1: ReadWrite<u32, GPFSEL1::Register>),
-        (0x08 => GPFSEL2: ReadWrite<u32>),
-        (0x0C => GPFSEL3: ReadWrite<u32>),
-        (0x10 => GPFSEL4: ReadWrite<u32>),
-        (0x14 => GPFSEL5: ReadWrite<u32>),
-        (0x18 => _reserved1),
-        (0x94 => GPPUD: ReadWrite<u32>),
+        (0x08 => _reserved2),
+        (0x94 => GPPUD: ReadWrite<u32, GPPUD::Register>),
         (0x98 => GPPUDCLK0: ReadWrite<u32, GPPUDCLK0::Register>),
-        (0x9C => GPPUDCLK1: ReadWrite<u32>),
-        (0xA0 => @END),
+        (0x9C => _reserved3),
+        (0xE4 => GPIO_PUP_PDN_CNTRL_REG0: ReadWrite<u32, GPIO_PUP_PDN_CNTRL_REG0::Register>),
+        (0xE8 => @END),
     }
 }
 
@@ -107,26 +136,58 @@ impl GPIOInner {
         }
     }
 
+    /// Disable pull-up/down on pins 14 and 15.
+    #[cfg(feature = "bsp_rpi3")]
+    fn disable_pud_14_15_bcm2837(&mut self) {
+        use crate::cpu;
+
+        // Make an educated guess for a good delay value (Sequence described in the BCM2837
+        // peripherals PDF).
+        //
+        // - According to Wikipedia, the fastest Pi3 clocks around 1.4 GHz.
+        // - The Linux 2837 GPIO driver waits 1 µs between the steps.
+        //
+        // So lets try to be on the safe side and default to 2000 cycles, which would equal 1 µs
+        // would the CPU be clocked at 2 GHz.
+        const DELAY: usize = 2000;
+
+        self.registers.GPPUD.write(GPPUD::PUD::Off);
+        cpu::spin_for_cycles(DELAY);
+
+        self.registers
+            .GPPUDCLK0
+            .write(GPPUDCLK0::PUDCLK15::AssertClock + GPPUDCLK0::PUDCLK14::AssertClock);
+        cpu::spin_for_cycles(DELAY);
+
+        self.registers.GPPUD.write(GPPUD::PUD::Off);
+        self.registers.GPPUDCLK0.set(0);
+    }
+
+    /// Disable pull-up/down on pins 14 and 15.
+    #[cfg(feature = "bsp_rpi4")]
+    fn disable_pud_14_15_bcm2711(&mut self) {
+        self.registers.GPIO_PUP_PDN_CNTRL_REG0.write(
+            GPIO_PUP_PDN_CNTRL_REG0::GPIO_PUP_PDN_CNTRL15::PullUp
+                + GPIO_PUP_PDN_CNTRL_REG0::GPIO_PUP_PDN_CNTRL14::PullUp,
+        );
+    }
+
     /// Map PL011 UART as standard output.
     ///
     /// TX to pin 14
     /// RX to pin 15
     pub fn map_pl011_uart(&mut self) {
-        // Map to pins.
+        // Select the UART on pins 14 and 15.
         self.registers
             .GPFSEL1
-            .modify(GPFSEL1::FSEL14::AltFunc0 + GPFSEL1::FSEL15::AltFunc0);
+            .modify(GPFSEL1::FSEL15::AltFunc0 + GPFSEL1::FSEL14::AltFunc0);
 
-        // Enable pins 14 and 15.
-        self.registers.GPPUD.set(0);
-        cpu::spin_for_cycles(150);
+        // Disable pull-up/down on pins 14 and 15.
+        #[cfg(feature = "bsp_rpi3")]
+        self.disable_pud_14_15_bcm2837();
 
-        self.registers
-            .GPPUDCLK0
-            .write(GPPUDCLK0::PUDCLK14::AssertClock + GPPUDCLK0::PUDCLK15::AssertClock);
-        cpu::spin_for_cycles(150);
-
-        self.registers.GPPUDCLK0.set(0);
+        #[cfg(feature = "bsp_rpi4")]
+        self.disable_pud_14_15_bcm2711();
     }
 }
 
diff --git a/07_uart_chainloader/README.md b/07_uart_chainloader/README.md
index 663bad83..efb9e008 100644
--- a/07_uart_chainloader/README.md
+++ b/07_uart_chainloader/README.md
@@ -194,7 +194,7 @@ diff -uNr 06_drivers_gpio_uart/src/_arch/aarch64/cpu.rs 07_uart_chainloader/src/
      } else {
          // If not core0, infinitely wait for events.
          wait_forever()
-@@ -54,3 +54,19 @@
+@@ -55,3 +55,19 @@
          asm::wfe()
      }
  }
diff --git a/07_uart_chainloader/demo_payload_rpi3.img b/07_uart_chainloader/demo_payload_rpi3.img
index 0e353b7dc74b4fd01860d01b33bebae20dabbaab..9adf8152f7447be4c0d35ec20c96f7c67c377510 100755
GIT binary patch
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c=T_rjsnzf*&seq@KlO08{zD#6CUVRE2@M|Xx&QzG

delta 3719
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diff --git a/07_uart_chainloader/demo_payload_rpi4.img b/07_uart_chainloader/demo_payload_rpi4.img
index 4cf8cb9f0a84c805df9c41512669bf2c19f87385..c3b1ede6cc6ba9075e528da9dfaa43ef960e33ed 100755
GIT binary patch
delta 4031
zcmZu!eNYtV8Gm+{<vsurjsp%fcLz~8jDjU_V*X$OHGui(keiw|AIE7(L_h_cW=z`d
zA<dKoHEv#~&DeH=v43PwlbD8NB!4ubnT)B?iA`%W`6mZXXOPn*s0o}VTz~KG9Z8z*
z%+2omywCeQzvuhCXw8{52bQSs2z1axo_{8q#0&GAEc%W6t@?Gz9myj)esHo}o09S(
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z1EtzjS(-j2k!FYN*6|{&<!Zf|!fn%~f}T)C{jwxzmrEsG0E0JNtVNqhdqgw=5@-}H
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zi8B8_K^c2>DdoOfL%l17eMO=Byc^=@Wzz2RrpNb#X+M=42l)5-L?sT;SohKm@x9>b
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z?N4;9>g*48^z7WVyWGdIZ|>h&*%#{Hxw)gSZ}-m5%ASs%9eulD%$rHMOOtw9@J62?
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sUAbjPUq>Z()#E+8DtmT3mJBp~RBYlaPRiee|2rs~AJIeXjiSo`0wSQZY5)KL

delta 3696
zcmZWreQZ<L6+iDi+p(PwCywpdPKxaWlGtfLTN<1&O?iZ(0waZ{)>zk8iOKpA650kT
ztsU!Z$fl(YRJ`3(?Yd2bqHR3)i>>KI`o|iYNuy$AwCm{h$22EwlM@3Yl$N+H^?vug
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diff --git a/07_uart_chainloader/src/_arch/aarch64/cpu.rs b/07_uart_chainloader/src/_arch/aarch64/cpu.rs
index 34cf2ab9..3121e75e 100644
--- a/07_uart_chainloader/src/_arch/aarch64/cpu.rs
+++ b/07_uart_chainloader/src/_arch/aarch64/cpu.rs
@@ -40,6 +40,7 @@ pub unsafe fn _start() -> ! {
 pub use asm::nop;
 
 /// Spin for `n` cycles.
+#[cfg(feature = "bsp_rpi3")]
 #[inline(always)]
 pub fn spin_for_cycles(n: usize) {
     for _ in 0..n {
diff --git a/07_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs b/07_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
index 0b01db4b..974ed70f 100644
--- a/07_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
+++ b/07_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
@@ -5,7 +5,7 @@
 //! GPIO Driver.
 
 use crate::{
-    bsp::device_driver::common::MMIODerefWrapper, cpu, driver, synchronization,
+    bsp::device_driver::common::MMIODerefWrapper, driver, synchronization,
     synchronization::NullLock,
 };
 use register::{mmio::*, register_bitfields, register_structs};
@@ -17,7 +17,8 @@ use register::{mmio::*, register_bitfields, register_structs};
 // GPIO registers.
 //
 // Descriptions taken from
-// https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
+// - https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
+// - https://datasheets.raspberrypi.org/bcm2711/bcm2711-peripherals.pdf
 register_bitfields! {
     u32,
 
@@ -39,7 +40,21 @@ register_bitfields! {
         ]
     ],
 
+    /// GPIO Pull-up/down Register
+    ///
+    /// BCM2837 only.
+    GPPUD [
+        /// Controls the actuation of the internal pull-up/down control line to ALL the GPIO pins.
+        PUD OFFSET(0) NUMBITS(2) [
+            Off = 0b00,
+            PullDown = 0b01,
+            PullUp = 0b10
+        ]
+    ],
+
     /// GPIO Pull-up/down Clock Register 0
+    ///
+    /// BCM2837 only.
     GPPUDCLK0 [
         /// Pin 15
         PUDCLK15 OFFSET(15) NUMBITS(1) [
@@ -52,23 +67,37 @@ register_bitfields! {
             NoEffect = 0,
             AssertClock = 1
         ]
+    ],
+
+    /// GPIO Pull-up / Pull-down Register 0
+    ///
+    /// BCM2711 only.
+    GPIO_PUP_PDN_CNTRL_REG0 [
+        /// Pin 15
+        GPIO_PUP_PDN_CNTRL15 OFFSET(30) NUMBITS(2) [
+            NoResistor = 0b00,
+            PullUp = 0b01
+        ],
+
+        /// Pin 14
+        GPIO_PUP_PDN_CNTRL14 OFFSET(28) NUMBITS(2) [
+            NoResistor = 0b00,
+            PullUp = 0b01
+        ]
     ]
 }
 
 register_structs! {
     #[allow(non_snake_case)]
     RegisterBlock {
-        (0x00 => GPFSEL0: ReadWrite<u32>),
+        (0x00 => _reserved1),
         (0x04 => GPFSEL1: ReadWrite<u32, GPFSEL1::Register>),
-        (0x08 => GPFSEL2: ReadWrite<u32>),
-        (0x0C => GPFSEL3: ReadWrite<u32>),
-        (0x10 => GPFSEL4: ReadWrite<u32>),
-        (0x14 => GPFSEL5: ReadWrite<u32>),
-        (0x18 => _reserved1),
-        (0x94 => GPPUD: ReadWrite<u32>),
+        (0x08 => _reserved2),
+        (0x94 => GPPUD: ReadWrite<u32, GPPUD::Register>),
         (0x98 => GPPUDCLK0: ReadWrite<u32, GPPUDCLK0::Register>),
-        (0x9C => GPPUDCLK1: ReadWrite<u32>),
-        (0xA0 => @END),
+        (0x9C => _reserved3),
+        (0xE4 => GPIO_PUP_PDN_CNTRL_REG0: ReadWrite<u32, GPIO_PUP_PDN_CNTRL_REG0::Register>),
+        (0xE8 => @END),
     }
 }
 
@@ -107,26 +136,58 @@ impl GPIOInner {
         }
     }
 
+    /// Disable pull-up/down on pins 14 and 15.
+    #[cfg(feature = "bsp_rpi3")]
+    fn disable_pud_14_15_bcm2837(&mut self) {
+        use crate::cpu;
+
+        // Make an educated guess for a good delay value (Sequence described in the BCM2837
+        // peripherals PDF).
+        //
+        // - According to Wikipedia, the fastest Pi3 clocks around 1.4 GHz.
+        // - The Linux 2837 GPIO driver waits 1 µs between the steps.
+        //
+        // So lets try to be on the safe side and default to 2000 cycles, which would equal 1 µs
+        // would the CPU be clocked at 2 GHz.
+        const DELAY: usize = 2000;
+
+        self.registers.GPPUD.write(GPPUD::PUD::Off);
+        cpu::spin_for_cycles(DELAY);
+
+        self.registers
+            .GPPUDCLK0
+            .write(GPPUDCLK0::PUDCLK15::AssertClock + GPPUDCLK0::PUDCLK14::AssertClock);
+        cpu::spin_for_cycles(DELAY);
+
+        self.registers.GPPUD.write(GPPUD::PUD::Off);
+        self.registers.GPPUDCLK0.set(0);
+    }
+
+    /// Disable pull-up/down on pins 14 and 15.
+    #[cfg(feature = "bsp_rpi4")]
+    fn disable_pud_14_15_bcm2711(&mut self) {
+        self.registers.GPIO_PUP_PDN_CNTRL_REG0.write(
+            GPIO_PUP_PDN_CNTRL_REG0::GPIO_PUP_PDN_CNTRL15::PullUp
+                + GPIO_PUP_PDN_CNTRL_REG0::GPIO_PUP_PDN_CNTRL14::PullUp,
+        );
+    }
+
     /// Map PL011 UART as standard output.
     ///
     /// TX to pin 14
     /// RX to pin 15
     pub fn map_pl011_uart(&mut self) {
-        // Map to pins.
+        // Select the UART on pins 14 and 15.
         self.registers
             .GPFSEL1
-            .modify(GPFSEL1::FSEL14::AltFunc0 + GPFSEL1::FSEL15::AltFunc0);
+            .modify(GPFSEL1::FSEL15::AltFunc0 + GPFSEL1::FSEL14::AltFunc0);
 
-        // Enable pins 14 and 15.
-        self.registers.GPPUD.set(0);
-        cpu::spin_for_cycles(150);
+        // Disable pull-up/down on pins 14 and 15.
+        #[cfg(feature = "bsp_rpi3")]
+        self.disable_pud_14_15_bcm2837();
 
-        self.registers
-            .GPPUDCLK0
-            .write(GPPUDCLK0::PUDCLK14::AssertClock + GPPUDCLK0::PUDCLK15::AssertClock);
-        cpu::spin_for_cycles(150);
-
-        self.registers.GPPUDCLK0.set(0);
+        #[cfg(feature = "bsp_rpi4")]
+        self.disable_pud_14_15_bcm2711();
     }
 }
 
diff --git a/08_timestamps/README.md b/08_timestamps/README.md
index e812e05b..73684f44 100644
--- a/08_timestamps/README.md
+++ b/08_timestamps/README.md
@@ -130,7 +130,23 @@ diff -uNr 07_uart_chainloader/src/_arch/aarch64/cpu.rs 08_timestamps/src/_arch/a
      } else {
          // If not core0, infinitely wait for events.
          wait_forever()
-@@ -54,19 +54,3 @@
+@@ -39,15 +39,6 @@
+
+ pub use asm::nop;
+
+-/// Spin for `n` cycles.
+-#[cfg(feature = "bsp_rpi3")]
+-#[inline(always)]
+-pub fn spin_for_cycles(n: usize) {
+-    for _ in 0..n {
+-        asm::nop();
+-    }
+-}
+-
+ /// Pause execution on the core.
+ #[inline(always)]
+ pub fn wait_forever() -> ! {
+@@ -55,19 +46,3 @@
          asm::wfe()
      }
  }
@@ -254,6 +270,42 @@ diff -uNr 07_uart_chainloader/src/_arch/aarch64/time.rs 08_timestamps/src/_arch/
 +    }
 +}
 
+diff -uNr 07_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 08_timestamps/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
+--- 07_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
++++ 08_timestamps/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
+@@ -139,25 +139,19 @@
+     /// Disable pull-up/down on pins 14 and 15.
+     #[cfg(feature = "bsp_rpi3")]
+     fn disable_pud_14_15_bcm2837(&mut self) {
+-        use crate::cpu;
++        use crate::{time, time::interface::TimeManager};
++        use core::time::Duration;
+
+-        // Make an educated guess for a good delay value (Sequence described in the BCM2837
+-        // peripherals PDF).
+-        //
+-        // - According to Wikipedia, the fastest Pi3 clocks around 1.4 GHz.
+-        // - The Linux 2837 GPIO driver waits 1 µs between the steps.
+-        //
+-        // So lets try to be on the safe side and default to 2000 cycles, which would equal 1 µs
+-        // would the CPU be clocked at 2 GHz.
+-        const DELAY: usize = 2000;
++        // The Linux 2837 GPIO driver waits 1 µs between the steps.
++        const DELAY: Duration = Duration::from_micros(1);
+
+         self.registers.GPPUD.write(GPPUD::PUD::Off);
+-        cpu::spin_for_cycles(DELAY);
++        time::time_manager().spin_for(DELAY);
+
+         self.registers
+             .GPPUDCLK0
+             .write(GPPUDCLK0::PUDCLK15::AssertClock + GPPUDCLK0::PUDCLK14::AssertClock);
+-        cpu::spin_for_cycles(DELAY);
++        time::time_manager().spin_for(DELAY);
+
+         self.registers.GPPUD.write(GPPUD::PUD::Off);
+         self.registers.GPPUDCLK0.set(0);
+
 diff -uNr 07_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 08_timestamps/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
 --- 07_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
 +++ 08_timestamps/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
diff --git a/08_timestamps/src/_arch/aarch64/cpu.rs b/08_timestamps/src/_arch/aarch64/cpu.rs
index 9b2da60d..3f502ee0 100644
--- a/08_timestamps/src/_arch/aarch64/cpu.rs
+++ b/08_timestamps/src/_arch/aarch64/cpu.rs
@@ -39,14 +39,6 @@ pub unsafe fn _start() -> ! {
 
 pub use asm::nop;
 
-/// Spin for `n` cycles.
-#[inline(always)]
-pub fn spin_for_cycles(n: usize) {
-    for _ in 0..n {
-        asm::nop();
-    }
-}
-
 /// Pause execution on the core.
 #[inline(always)]
 pub fn wait_forever() -> ! {
diff --git a/08_timestamps/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs b/08_timestamps/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
index 0b01db4b..e06cbc7f 100644
--- a/08_timestamps/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
+++ b/08_timestamps/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
@@ -5,7 +5,7 @@
 //! GPIO Driver.
 
 use crate::{
-    bsp::device_driver::common::MMIODerefWrapper, cpu, driver, synchronization,
+    bsp::device_driver::common::MMIODerefWrapper, driver, synchronization,
     synchronization::NullLock,
 };
 use register::{mmio::*, register_bitfields, register_structs};
@@ -17,7 +17,8 @@ use register::{mmio::*, register_bitfields, register_structs};
 // GPIO registers.
 //
 // Descriptions taken from
-// https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
+// - https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
+// - https://datasheets.raspberrypi.org/bcm2711/bcm2711-peripherals.pdf
 register_bitfields! {
     u32,
 
@@ -39,7 +40,21 @@ register_bitfields! {
         ]
     ],
 
+    /// GPIO Pull-up/down Register
+    ///
+    /// BCM2837 only.
+    GPPUD [
+        /// Controls the actuation of the internal pull-up/down control line to ALL the GPIO pins.
+        PUD OFFSET(0) NUMBITS(2) [
+            Off = 0b00,
+            PullDown = 0b01,
+            PullUp = 0b10
+        ]
+    ],
+
     /// GPIO Pull-up/down Clock Register 0
+    ///
+    /// BCM2837 only.
     GPPUDCLK0 [
         /// Pin 15
         PUDCLK15 OFFSET(15) NUMBITS(1) [
@@ -52,23 +67,37 @@ register_bitfields! {
             NoEffect = 0,
             AssertClock = 1
         ]
+    ],
+
+    /// GPIO Pull-up / Pull-down Register 0
+    ///
+    /// BCM2711 only.
+    GPIO_PUP_PDN_CNTRL_REG0 [
+        /// Pin 15
+        GPIO_PUP_PDN_CNTRL15 OFFSET(30) NUMBITS(2) [
+            NoResistor = 0b00,
+            PullUp = 0b01
+        ],
+
+        /// Pin 14
+        GPIO_PUP_PDN_CNTRL14 OFFSET(28) NUMBITS(2) [
+            NoResistor = 0b00,
+            PullUp = 0b01
+        ]
     ]
 }
 
 register_structs! {
     #[allow(non_snake_case)]
     RegisterBlock {
-        (0x00 => GPFSEL0: ReadWrite<u32>),
+        (0x00 => _reserved1),
         (0x04 => GPFSEL1: ReadWrite<u32, GPFSEL1::Register>),
-        (0x08 => GPFSEL2: ReadWrite<u32>),
-        (0x0C => GPFSEL3: ReadWrite<u32>),
-        (0x10 => GPFSEL4: ReadWrite<u32>),
-        (0x14 => GPFSEL5: ReadWrite<u32>),
-        (0x18 => _reserved1),
-        (0x94 => GPPUD: ReadWrite<u32>),
+        (0x08 => _reserved2),
+        (0x94 => GPPUD: ReadWrite<u32, GPPUD::Register>),
         (0x98 => GPPUDCLK0: ReadWrite<u32, GPPUDCLK0::Register>),
-        (0x9C => GPPUDCLK1: ReadWrite<u32>),
-        (0xA0 => @END),
+        (0x9C => _reserved3),
+        (0xE4 => GPIO_PUP_PDN_CNTRL_REG0: ReadWrite<u32, GPIO_PUP_PDN_CNTRL_REG0::Register>),
+        (0xE8 => @END),
     }
 }
 
@@ -107,26 +136,52 @@ impl GPIOInner {
         }
     }
 
+    /// Disable pull-up/down on pins 14 and 15.
+    #[cfg(feature = "bsp_rpi3")]
+    fn disable_pud_14_15_bcm2837(&mut self) {
+        use crate::{time, time::interface::TimeManager};
+        use core::time::Duration;
+
+        // The Linux 2837 GPIO driver waits 1 µs between the steps.
+        const DELAY: Duration = Duration::from_micros(1);
+
+        self.registers.GPPUD.write(GPPUD::PUD::Off);
+        time::time_manager().spin_for(DELAY);
+
+        self.registers
+            .GPPUDCLK0
+            .write(GPPUDCLK0::PUDCLK15::AssertClock + GPPUDCLK0::PUDCLK14::AssertClock);
+        time::time_manager().spin_for(DELAY);
+
+        self.registers.GPPUD.write(GPPUD::PUD::Off);
+        self.registers.GPPUDCLK0.set(0);
+    }
+
+    /// Disable pull-up/down on pins 14 and 15.
+    #[cfg(feature = "bsp_rpi4")]
+    fn disable_pud_14_15_bcm2711(&mut self) {
+        self.registers.GPIO_PUP_PDN_CNTRL_REG0.write(
+            GPIO_PUP_PDN_CNTRL_REG0::GPIO_PUP_PDN_CNTRL15::PullUp
+                + GPIO_PUP_PDN_CNTRL_REG0::GPIO_PUP_PDN_CNTRL14::PullUp,
+        );
+    }
+
     /// Map PL011 UART as standard output.
     ///
     /// TX to pin 14
     /// RX to pin 15
     pub fn map_pl011_uart(&mut self) {
-        // Map to pins.
+        // Select the UART on pins 14 and 15.
         self.registers
             .GPFSEL1
-            .modify(GPFSEL1::FSEL14::AltFunc0 + GPFSEL1::FSEL15::AltFunc0);
+            .modify(GPFSEL1::FSEL15::AltFunc0 + GPFSEL1::FSEL14::AltFunc0);
 
-        // Enable pins 14 and 15.
-        self.registers.GPPUD.set(0);
-        cpu::spin_for_cycles(150);
+        // Disable pull-up/down on pins 14 and 15.
+        #[cfg(feature = "bsp_rpi3")]
+        self.disable_pud_14_15_bcm2837();
 
-        self.registers
-            .GPPUDCLK0
-            .write(GPPUDCLK0::PUDCLK14::AssertClock + GPPUDCLK0::PUDCLK15::AssertClock);
-        cpu::spin_for_cycles(150);
-
-        self.registers.GPPUDCLK0.set(0);
+        #[cfg(feature = "bsp_rpi4")]
+        self.disable_pud_14_15_bcm2711();
     }
 }
 
diff --git a/09_hw_debug_JTAG/src/_arch/aarch64/cpu.rs b/09_hw_debug_JTAG/src/_arch/aarch64/cpu.rs
index 9b2da60d..3f502ee0 100644
--- a/09_hw_debug_JTAG/src/_arch/aarch64/cpu.rs
+++ b/09_hw_debug_JTAG/src/_arch/aarch64/cpu.rs
@@ -39,14 +39,6 @@ pub unsafe fn _start() -> ! {
 
 pub use asm::nop;
 
-/// Spin for `n` cycles.
-#[inline(always)]
-pub fn spin_for_cycles(n: usize) {
-    for _ in 0..n {
-        asm::nop();
-    }
-}
-
 /// Pause execution on the core.
 #[inline(always)]
 pub fn wait_forever() -> ! {
diff --git a/09_hw_debug_JTAG/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs b/09_hw_debug_JTAG/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
index 0b01db4b..e06cbc7f 100644
--- a/09_hw_debug_JTAG/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
+++ b/09_hw_debug_JTAG/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
@@ -5,7 +5,7 @@
 //! GPIO Driver.
 
 use crate::{
-    bsp::device_driver::common::MMIODerefWrapper, cpu, driver, synchronization,
+    bsp::device_driver::common::MMIODerefWrapper, driver, synchronization,
     synchronization::NullLock,
 };
 use register::{mmio::*, register_bitfields, register_structs};
@@ -17,7 +17,8 @@ use register::{mmio::*, register_bitfields, register_structs};
 // GPIO registers.
 //
 // Descriptions taken from
-// https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
+// - https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
+// - https://datasheets.raspberrypi.org/bcm2711/bcm2711-peripherals.pdf
 register_bitfields! {
     u32,
 
@@ -39,7 +40,21 @@ register_bitfields! {
         ]
     ],
 
+    /// GPIO Pull-up/down Register
+    ///
+    /// BCM2837 only.
+    GPPUD [
+        /// Controls the actuation of the internal pull-up/down control line to ALL the GPIO pins.
+        PUD OFFSET(0) NUMBITS(2) [
+            Off = 0b00,
+            PullDown = 0b01,
+            PullUp = 0b10
+        ]
+    ],
+
     /// GPIO Pull-up/down Clock Register 0
+    ///
+    /// BCM2837 only.
     GPPUDCLK0 [
         /// Pin 15
         PUDCLK15 OFFSET(15) NUMBITS(1) [
@@ -52,23 +67,37 @@ register_bitfields! {
             NoEffect = 0,
             AssertClock = 1
         ]
+    ],
+
+    /// GPIO Pull-up / Pull-down Register 0
+    ///
+    /// BCM2711 only.
+    GPIO_PUP_PDN_CNTRL_REG0 [
+        /// Pin 15
+        GPIO_PUP_PDN_CNTRL15 OFFSET(30) NUMBITS(2) [
+            NoResistor = 0b00,
+            PullUp = 0b01
+        ],
+
+        /// Pin 14
+        GPIO_PUP_PDN_CNTRL14 OFFSET(28) NUMBITS(2) [
+            NoResistor = 0b00,
+            PullUp = 0b01
+        ]
     ]
 }
 
 register_structs! {
     #[allow(non_snake_case)]
     RegisterBlock {
-        (0x00 => GPFSEL0: ReadWrite<u32>),
+        (0x00 => _reserved1),
         (0x04 => GPFSEL1: ReadWrite<u32, GPFSEL1::Register>),
-        (0x08 => GPFSEL2: ReadWrite<u32>),
-        (0x0C => GPFSEL3: ReadWrite<u32>),
-        (0x10 => GPFSEL4: ReadWrite<u32>),
-        (0x14 => GPFSEL5: ReadWrite<u32>),
-        (0x18 => _reserved1),
-        (0x94 => GPPUD: ReadWrite<u32>),
+        (0x08 => _reserved2),
+        (0x94 => GPPUD: ReadWrite<u32, GPPUD::Register>),
         (0x98 => GPPUDCLK0: ReadWrite<u32, GPPUDCLK0::Register>),
-        (0x9C => GPPUDCLK1: ReadWrite<u32>),
-        (0xA0 => @END),
+        (0x9C => _reserved3),
+        (0xE4 => GPIO_PUP_PDN_CNTRL_REG0: ReadWrite<u32, GPIO_PUP_PDN_CNTRL_REG0::Register>),
+        (0xE8 => @END),
     }
 }
 
@@ -107,26 +136,52 @@ impl GPIOInner {
         }
     }
 
+    /// Disable pull-up/down on pins 14 and 15.
+    #[cfg(feature = "bsp_rpi3")]
+    fn disable_pud_14_15_bcm2837(&mut self) {
+        use crate::{time, time::interface::TimeManager};
+        use core::time::Duration;
+
+        // The Linux 2837 GPIO driver waits 1 µs between the steps.
+        const DELAY: Duration = Duration::from_micros(1);
+
+        self.registers.GPPUD.write(GPPUD::PUD::Off);
+        time::time_manager().spin_for(DELAY);
+
+        self.registers
+            .GPPUDCLK0
+            .write(GPPUDCLK0::PUDCLK15::AssertClock + GPPUDCLK0::PUDCLK14::AssertClock);
+        time::time_manager().spin_for(DELAY);
+
+        self.registers.GPPUD.write(GPPUD::PUD::Off);
+        self.registers.GPPUDCLK0.set(0);
+    }
+
+    /// Disable pull-up/down on pins 14 and 15.
+    #[cfg(feature = "bsp_rpi4")]
+    fn disable_pud_14_15_bcm2711(&mut self) {
+        self.registers.GPIO_PUP_PDN_CNTRL_REG0.write(
+            GPIO_PUP_PDN_CNTRL_REG0::GPIO_PUP_PDN_CNTRL15::PullUp
+                + GPIO_PUP_PDN_CNTRL_REG0::GPIO_PUP_PDN_CNTRL14::PullUp,
+        );
+    }
+
     /// Map PL011 UART as standard output.
     ///
     /// TX to pin 14
     /// RX to pin 15
     pub fn map_pl011_uart(&mut self) {
-        // Map to pins.
+        // Select the UART on pins 14 and 15.
         self.registers
             .GPFSEL1
-            .modify(GPFSEL1::FSEL14::AltFunc0 + GPFSEL1::FSEL15::AltFunc0);
+            .modify(GPFSEL1::FSEL15::AltFunc0 + GPFSEL1::FSEL14::AltFunc0);
 
-        // Enable pins 14 and 15.
-        self.registers.GPPUD.set(0);
-        cpu::spin_for_cycles(150);
+        // Disable pull-up/down on pins 14 and 15.
+        #[cfg(feature = "bsp_rpi3")]
+        self.disable_pud_14_15_bcm2837();
 
-        self.registers
-            .GPPUDCLK0
-            .write(GPPUDCLK0::PUDCLK14::AssertClock + GPPUDCLK0::PUDCLK15::AssertClock);
-        cpu::spin_for_cycles(150);
-
-        self.registers.GPPUDCLK0.set(0);
+        #[cfg(feature = "bsp_rpi4")]
+        self.disable_pud_14_15_bcm2711();
     }
 }
 
diff --git a/10_privilege_level/src/_arch/aarch64/cpu.rs b/10_privilege_level/src/_arch/aarch64/cpu.rs
index ab7c6047..3e5e5753 100644
--- a/10_privilege_level/src/_arch/aarch64/cpu.rs
+++ b/10_privilege_level/src/_arch/aarch64/cpu.rs
@@ -80,14 +80,6 @@ unsafe fn el2_to_el1_transition() -> ! {
 
 pub use asm::nop;
 
-/// Spin for `n` cycles.
-#[inline(always)]
-pub fn spin_for_cycles(n: usize) {
-    for _ in 0..n {
-        asm::nop();
-    }
-}
-
 /// Pause execution on the core.
 #[inline(always)]
 pub fn wait_forever() -> ! {
diff --git a/10_privilege_level/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs b/10_privilege_level/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
index 0b01db4b..e06cbc7f 100644
--- a/10_privilege_level/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
+++ b/10_privilege_level/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
@@ -5,7 +5,7 @@
 //! GPIO Driver.
 
 use crate::{
-    bsp::device_driver::common::MMIODerefWrapper, cpu, driver, synchronization,
+    bsp::device_driver::common::MMIODerefWrapper, driver, synchronization,
     synchronization::NullLock,
 };
 use register::{mmio::*, register_bitfields, register_structs};
@@ -17,7 +17,8 @@ use register::{mmio::*, register_bitfields, register_structs};
 // GPIO registers.
 //
 // Descriptions taken from
-// https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
+// - https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
+// - https://datasheets.raspberrypi.org/bcm2711/bcm2711-peripherals.pdf
 register_bitfields! {
     u32,
 
@@ -39,7 +40,21 @@ register_bitfields! {
         ]
     ],
 
+    /// GPIO Pull-up/down Register
+    ///
+    /// BCM2837 only.
+    GPPUD [
+        /// Controls the actuation of the internal pull-up/down control line to ALL the GPIO pins.
+        PUD OFFSET(0) NUMBITS(2) [
+            Off = 0b00,
+            PullDown = 0b01,
+            PullUp = 0b10
+        ]
+    ],
+
     /// GPIO Pull-up/down Clock Register 0
+    ///
+    /// BCM2837 only.
     GPPUDCLK0 [
         /// Pin 15
         PUDCLK15 OFFSET(15) NUMBITS(1) [
@@ -52,23 +67,37 @@ register_bitfields! {
             NoEffect = 0,
             AssertClock = 1
         ]
+    ],
+
+    /// GPIO Pull-up / Pull-down Register 0
+    ///
+    /// BCM2711 only.
+    GPIO_PUP_PDN_CNTRL_REG0 [
+        /// Pin 15
+        GPIO_PUP_PDN_CNTRL15 OFFSET(30) NUMBITS(2) [
+            NoResistor = 0b00,
+            PullUp = 0b01
+        ],
+
+        /// Pin 14
+        GPIO_PUP_PDN_CNTRL14 OFFSET(28) NUMBITS(2) [
+            NoResistor = 0b00,
+            PullUp = 0b01
+        ]
     ]
 }
 
 register_structs! {
     #[allow(non_snake_case)]
     RegisterBlock {
-        (0x00 => GPFSEL0: ReadWrite<u32>),
+        (0x00 => _reserved1),
         (0x04 => GPFSEL1: ReadWrite<u32, GPFSEL1::Register>),
-        (0x08 => GPFSEL2: ReadWrite<u32>),
-        (0x0C => GPFSEL3: ReadWrite<u32>),
-        (0x10 => GPFSEL4: ReadWrite<u32>),
-        (0x14 => GPFSEL5: ReadWrite<u32>),
-        (0x18 => _reserved1),
-        (0x94 => GPPUD: ReadWrite<u32>),
+        (0x08 => _reserved2),
+        (0x94 => GPPUD: ReadWrite<u32, GPPUD::Register>),
         (0x98 => GPPUDCLK0: ReadWrite<u32, GPPUDCLK0::Register>),
-        (0x9C => GPPUDCLK1: ReadWrite<u32>),
-        (0xA0 => @END),
+        (0x9C => _reserved3),
+        (0xE4 => GPIO_PUP_PDN_CNTRL_REG0: ReadWrite<u32, GPIO_PUP_PDN_CNTRL_REG0::Register>),
+        (0xE8 => @END),
     }
 }
 
@@ -107,26 +136,52 @@ impl GPIOInner {
         }
     }
 
+    /// Disable pull-up/down on pins 14 and 15.
+    #[cfg(feature = "bsp_rpi3")]
+    fn disable_pud_14_15_bcm2837(&mut self) {
+        use crate::{time, time::interface::TimeManager};
+        use core::time::Duration;
+
+        // The Linux 2837 GPIO driver waits 1 µs between the steps.
+        const DELAY: Duration = Duration::from_micros(1);
+
+        self.registers.GPPUD.write(GPPUD::PUD::Off);
+        time::time_manager().spin_for(DELAY);
+
+        self.registers
+            .GPPUDCLK0
+            .write(GPPUDCLK0::PUDCLK15::AssertClock + GPPUDCLK0::PUDCLK14::AssertClock);
+        time::time_manager().spin_for(DELAY);
+
+        self.registers.GPPUD.write(GPPUD::PUD::Off);
+        self.registers.GPPUDCLK0.set(0);
+    }
+
+    /// Disable pull-up/down on pins 14 and 15.
+    #[cfg(feature = "bsp_rpi4")]
+    fn disable_pud_14_15_bcm2711(&mut self) {
+        self.registers.GPIO_PUP_PDN_CNTRL_REG0.write(
+            GPIO_PUP_PDN_CNTRL_REG0::GPIO_PUP_PDN_CNTRL15::PullUp
+                + GPIO_PUP_PDN_CNTRL_REG0::GPIO_PUP_PDN_CNTRL14::PullUp,
+        );
+    }
+
     /// Map PL011 UART as standard output.
     ///
     /// TX to pin 14
     /// RX to pin 15
     pub fn map_pl011_uart(&mut self) {
-        // Map to pins.
+        // Select the UART on pins 14 and 15.
         self.registers
             .GPFSEL1
-            .modify(GPFSEL1::FSEL14::AltFunc0 + GPFSEL1::FSEL15::AltFunc0);
+            .modify(GPFSEL1::FSEL15::AltFunc0 + GPFSEL1::FSEL14::AltFunc0);
 
-        // Enable pins 14 and 15.
-        self.registers.GPPUD.set(0);
-        cpu::spin_for_cycles(150);
+        // Disable pull-up/down on pins 14 and 15.
+        #[cfg(feature = "bsp_rpi3")]
+        self.disable_pud_14_15_bcm2837();
 
-        self.registers
-            .GPPUDCLK0
-            .write(GPPUDCLK0::PUDCLK14::AssertClock + GPPUDCLK0::PUDCLK15::AssertClock);
-        cpu::spin_for_cycles(150);
-
-        self.registers.GPPUDCLK0.set(0);
+        #[cfg(feature = "bsp_rpi4")]
+        self.disable_pud_14_15_bcm2711();
     }
 }
 
diff --git a/11_virtual_mem_part1_identity_mapping/src/_arch/aarch64/cpu.rs b/11_virtual_mem_part1_identity_mapping/src/_arch/aarch64/cpu.rs
index ab7c6047..3e5e5753 100644
--- a/11_virtual_mem_part1_identity_mapping/src/_arch/aarch64/cpu.rs
+++ b/11_virtual_mem_part1_identity_mapping/src/_arch/aarch64/cpu.rs
@@ -80,14 +80,6 @@ unsafe fn el2_to_el1_transition() -> ! {
 
 pub use asm::nop;
 
-/// Spin for `n` cycles.
-#[inline(always)]
-pub fn spin_for_cycles(n: usize) {
-    for _ in 0..n {
-        asm::nop();
-    }
-}
-
 /// Pause execution on the core.
 #[inline(always)]
 pub fn wait_forever() -> ! {
diff --git a/11_virtual_mem_part1_identity_mapping/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs b/11_virtual_mem_part1_identity_mapping/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
index 0b01db4b..e06cbc7f 100644
--- a/11_virtual_mem_part1_identity_mapping/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
+++ b/11_virtual_mem_part1_identity_mapping/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
@@ -5,7 +5,7 @@
 //! GPIO Driver.
 
 use crate::{
-    bsp::device_driver::common::MMIODerefWrapper, cpu, driver, synchronization,
+    bsp::device_driver::common::MMIODerefWrapper, driver, synchronization,
     synchronization::NullLock,
 };
 use register::{mmio::*, register_bitfields, register_structs};
@@ -17,7 +17,8 @@ use register::{mmio::*, register_bitfields, register_structs};
 // GPIO registers.
 //
 // Descriptions taken from
-// https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
+// - https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
+// - https://datasheets.raspberrypi.org/bcm2711/bcm2711-peripherals.pdf
 register_bitfields! {
     u32,
 
@@ -39,7 +40,21 @@ register_bitfields! {
         ]
     ],
 
+    /// GPIO Pull-up/down Register
+    ///
+    /// BCM2837 only.
+    GPPUD [
+        /// Controls the actuation of the internal pull-up/down control line to ALL the GPIO pins.
+        PUD OFFSET(0) NUMBITS(2) [
+            Off = 0b00,
+            PullDown = 0b01,
+            PullUp = 0b10
+        ]
+    ],
+
     /// GPIO Pull-up/down Clock Register 0
+    ///
+    /// BCM2837 only.
     GPPUDCLK0 [
         /// Pin 15
         PUDCLK15 OFFSET(15) NUMBITS(1) [
@@ -52,23 +67,37 @@ register_bitfields! {
             NoEffect = 0,
             AssertClock = 1
         ]
+    ],
+
+    /// GPIO Pull-up / Pull-down Register 0
+    ///
+    /// BCM2711 only.
+    GPIO_PUP_PDN_CNTRL_REG0 [
+        /// Pin 15
+        GPIO_PUP_PDN_CNTRL15 OFFSET(30) NUMBITS(2) [
+            NoResistor = 0b00,
+            PullUp = 0b01
+        ],
+
+        /// Pin 14
+        GPIO_PUP_PDN_CNTRL14 OFFSET(28) NUMBITS(2) [
+            NoResistor = 0b00,
+            PullUp = 0b01
+        ]
     ]
 }
 
 register_structs! {
     #[allow(non_snake_case)]
     RegisterBlock {
-        (0x00 => GPFSEL0: ReadWrite<u32>),
+        (0x00 => _reserved1),
         (0x04 => GPFSEL1: ReadWrite<u32, GPFSEL1::Register>),
-        (0x08 => GPFSEL2: ReadWrite<u32>),
-        (0x0C => GPFSEL3: ReadWrite<u32>),
-        (0x10 => GPFSEL4: ReadWrite<u32>),
-        (0x14 => GPFSEL5: ReadWrite<u32>),
-        (0x18 => _reserved1),
-        (0x94 => GPPUD: ReadWrite<u32>),
+        (0x08 => _reserved2),
+        (0x94 => GPPUD: ReadWrite<u32, GPPUD::Register>),
         (0x98 => GPPUDCLK0: ReadWrite<u32, GPPUDCLK0::Register>),
-        (0x9C => GPPUDCLK1: ReadWrite<u32>),
-        (0xA0 => @END),
+        (0x9C => _reserved3),
+        (0xE4 => GPIO_PUP_PDN_CNTRL_REG0: ReadWrite<u32, GPIO_PUP_PDN_CNTRL_REG0::Register>),
+        (0xE8 => @END),
     }
 }
 
@@ -107,26 +136,52 @@ impl GPIOInner {
         }
     }
 
+    /// Disable pull-up/down on pins 14 and 15.
+    #[cfg(feature = "bsp_rpi3")]
+    fn disable_pud_14_15_bcm2837(&mut self) {
+        use crate::{time, time::interface::TimeManager};
+        use core::time::Duration;
+
+        // The Linux 2837 GPIO driver waits 1 µs between the steps.
+        const DELAY: Duration = Duration::from_micros(1);
+
+        self.registers.GPPUD.write(GPPUD::PUD::Off);
+        time::time_manager().spin_for(DELAY);
+
+        self.registers
+            .GPPUDCLK0
+            .write(GPPUDCLK0::PUDCLK15::AssertClock + GPPUDCLK0::PUDCLK14::AssertClock);
+        time::time_manager().spin_for(DELAY);
+
+        self.registers.GPPUD.write(GPPUD::PUD::Off);
+        self.registers.GPPUDCLK0.set(0);
+    }
+
+    /// Disable pull-up/down on pins 14 and 15.
+    #[cfg(feature = "bsp_rpi4")]
+    fn disable_pud_14_15_bcm2711(&mut self) {
+        self.registers.GPIO_PUP_PDN_CNTRL_REG0.write(
+            GPIO_PUP_PDN_CNTRL_REG0::GPIO_PUP_PDN_CNTRL15::PullUp
+                + GPIO_PUP_PDN_CNTRL_REG0::GPIO_PUP_PDN_CNTRL14::PullUp,
+        );
+    }
+
     /// Map PL011 UART as standard output.
     ///
     /// TX to pin 14
     /// RX to pin 15
     pub fn map_pl011_uart(&mut self) {
-        // Map to pins.
+        // Select the UART on pins 14 and 15.
         self.registers
             .GPFSEL1
-            .modify(GPFSEL1::FSEL14::AltFunc0 + GPFSEL1::FSEL15::AltFunc0);
+            .modify(GPFSEL1::FSEL15::AltFunc0 + GPFSEL1::FSEL14::AltFunc0);
 
-        // Enable pins 14 and 15.
-        self.registers.GPPUD.set(0);
-        cpu::spin_for_cycles(150);
+        // Disable pull-up/down on pins 14 and 15.
+        #[cfg(feature = "bsp_rpi3")]
+        self.disable_pud_14_15_bcm2837();
 
-        self.registers
-            .GPPUDCLK0
-            .write(GPPUDCLK0::PUDCLK14::AssertClock + GPPUDCLK0::PUDCLK15::AssertClock);
-        cpu::spin_for_cycles(150);
-
-        self.registers.GPPUDCLK0.set(0);
+        #[cfg(feature = "bsp_rpi4")]
+        self.disable_pud_14_15_bcm2711();
     }
 }
 
diff --git a/12_exceptions_part1_groundwork/src/_arch/aarch64/cpu.rs b/12_exceptions_part1_groundwork/src/_arch/aarch64/cpu.rs
index ab7c6047..3e5e5753 100644
--- a/12_exceptions_part1_groundwork/src/_arch/aarch64/cpu.rs
+++ b/12_exceptions_part1_groundwork/src/_arch/aarch64/cpu.rs
@@ -80,14 +80,6 @@ unsafe fn el2_to_el1_transition() -> ! {
 
 pub use asm::nop;
 
-/// Spin for `n` cycles.
-#[inline(always)]
-pub fn spin_for_cycles(n: usize) {
-    for _ in 0..n {
-        asm::nop();
-    }
-}
-
 /// Pause execution on the core.
 #[inline(always)]
 pub fn wait_forever() -> ! {
diff --git a/12_exceptions_part1_groundwork/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs b/12_exceptions_part1_groundwork/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
index 0b01db4b..e06cbc7f 100644
--- a/12_exceptions_part1_groundwork/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
+++ b/12_exceptions_part1_groundwork/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
@@ -5,7 +5,7 @@
 //! GPIO Driver.
 
 use crate::{
-    bsp::device_driver::common::MMIODerefWrapper, cpu, driver, synchronization,
+    bsp::device_driver::common::MMIODerefWrapper, driver, synchronization,
     synchronization::NullLock,
 };
 use register::{mmio::*, register_bitfields, register_structs};
@@ -17,7 +17,8 @@ use register::{mmio::*, register_bitfields, register_structs};
 // GPIO registers.
 //
 // Descriptions taken from
-// https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
+// - https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
+// - https://datasheets.raspberrypi.org/bcm2711/bcm2711-peripherals.pdf
 register_bitfields! {
     u32,
 
@@ -39,7 +40,21 @@ register_bitfields! {
         ]
     ],
 
+    /// GPIO Pull-up/down Register
+    ///
+    /// BCM2837 only.
+    GPPUD [
+        /// Controls the actuation of the internal pull-up/down control line to ALL the GPIO pins.
+        PUD OFFSET(0) NUMBITS(2) [
+            Off = 0b00,
+            PullDown = 0b01,
+            PullUp = 0b10
+        ]
+    ],
+
     /// GPIO Pull-up/down Clock Register 0
+    ///
+    /// BCM2837 only.
     GPPUDCLK0 [
         /// Pin 15
         PUDCLK15 OFFSET(15) NUMBITS(1) [
@@ -52,23 +67,37 @@ register_bitfields! {
             NoEffect = 0,
             AssertClock = 1
         ]
+    ],
+
+    /// GPIO Pull-up / Pull-down Register 0
+    ///
+    /// BCM2711 only.
+    GPIO_PUP_PDN_CNTRL_REG0 [
+        /// Pin 15
+        GPIO_PUP_PDN_CNTRL15 OFFSET(30) NUMBITS(2) [
+            NoResistor = 0b00,
+            PullUp = 0b01
+        ],
+
+        /// Pin 14
+        GPIO_PUP_PDN_CNTRL14 OFFSET(28) NUMBITS(2) [
+            NoResistor = 0b00,
+            PullUp = 0b01
+        ]
     ]
 }
 
 register_structs! {
     #[allow(non_snake_case)]
     RegisterBlock {
-        (0x00 => GPFSEL0: ReadWrite<u32>),
+        (0x00 => _reserved1),
         (0x04 => GPFSEL1: ReadWrite<u32, GPFSEL1::Register>),
-        (0x08 => GPFSEL2: ReadWrite<u32>),
-        (0x0C => GPFSEL3: ReadWrite<u32>),
-        (0x10 => GPFSEL4: ReadWrite<u32>),
-        (0x14 => GPFSEL5: ReadWrite<u32>),
-        (0x18 => _reserved1),
-        (0x94 => GPPUD: ReadWrite<u32>),
+        (0x08 => _reserved2),
+        (0x94 => GPPUD: ReadWrite<u32, GPPUD::Register>),
         (0x98 => GPPUDCLK0: ReadWrite<u32, GPPUDCLK0::Register>),
-        (0x9C => GPPUDCLK1: ReadWrite<u32>),
-        (0xA0 => @END),
+        (0x9C => _reserved3),
+        (0xE4 => GPIO_PUP_PDN_CNTRL_REG0: ReadWrite<u32, GPIO_PUP_PDN_CNTRL_REG0::Register>),
+        (0xE8 => @END),
     }
 }
 
@@ -107,26 +136,52 @@ impl GPIOInner {
         }
     }
 
+    /// Disable pull-up/down on pins 14 and 15.
+    #[cfg(feature = "bsp_rpi3")]
+    fn disable_pud_14_15_bcm2837(&mut self) {
+        use crate::{time, time::interface::TimeManager};
+        use core::time::Duration;
+
+        // The Linux 2837 GPIO driver waits 1 µs between the steps.
+        const DELAY: Duration = Duration::from_micros(1);
+
+        self.registers.GPPUD.write(GPPUD::PUD::Off);
+        time::time_manager().spin_for(DELAY);
+
+        self.registers
+            .GPPUDCLK0
+            .write(GPPUDCLK0::PUDCLK15::AssertClock + GPPUDCLK0::PUDCLK14::AssertClock);
+        time::time_manager().spin_for(DELAY);
+
+        self.registers.GPPUD.write(GPPUD::PUD::Off);
+        self.registers.GPPUDCLK0.set(0);
+    }
+
+    /// Disable pull-up/down on pins 14 and 15.
+    #[cfg(feature = "bsp_rpi4")]
+    fn disable_pud_14_15_bcm2711(&mut self) {
+        self.registers.GPIO_PUP_PDN_CNTRL_REG0.write(
+            GPIO_PUP_PDN_CNTRL_REG0::GPIO_PUP_PDN_CNTRL15::PullUp
+                + GPIO_PUP_PDN_CNTRL_REG0::GPIO_PUP_PDN_CNTRL14::PullUp,
+        );
+    }
+
     /// Map PL011 UART as standard output.
     ///
     /// TX to pin 14
     /// RX to pin 15
     pub fn map_pl011_uart(&mut self) {
-        // Map to pins.
+        // Select the UART on pins 14 and 15.
         self.registers
             .GPFSEL1
-            .modify(GPFSEL1::FSEL14::AltFunc0 + GPFSEL1::FSEL15::AltFunc0);
+            .modify(GPFSEL1::FSEL15::AltFunc0 + GPFSEL1::FSEL14::AltFunc0);
 
-        // Enable pins 14 and 15.
-        self.registers.GPPUD.set(0);
-        cpu::spin_for_cycles(150);
+        // Disable pull-up/down on pins 14 and 15.
+        #[cfg(feature = "bsp_rpi3")]
+        self.disable_pud_14_15_bcm2837();
 
-        self.registers
-            .GPPUDCLK0
-            .write(GPPUDCLK0::PUDCLK14::AssertClock + GPPUDCLK0::PUDCLK15::AssertClock);
-        cpu::spin_for_cycles(150);
-
-        self.registers.GPPUDCLK0.set(0);
+        #[cfg(feature = "bsp_rpi4")]
+        self.disable_pud_14_15_bcm2711();
     }
 }
 
diff --git a/13_integrated_testing/README.md b/13_integrated_testing/README.md
index 68460d7b..50b9436b 100644
--- a/13_integrated_testing/README.md
+++ b/13_integrated_testing/README.md
@@ -935,7 +935,7 @@ diff -uNr 12_exceptions_part1_groundwork/Makefile 13_integrated_testing/Makefile
 diff -uNr 12_exceptions_part1_groundwork/src/_arch/aarch64/cpu.rs 13_integrated_testing/src/_arch/aarch64/cpu.rs
 --- 12_exceptions_part1_groundwork/src/_arch/aarch64/cpu.rs
 +++ 13_integrated_testing/src/_arch/aarch64/cpu.rs
-@@ -95,3 +95,20 @@
+@@ -87,3 +87,20 @@
          asm::wfe()
      }
  }
diff --git a/13_integrated_testing/src/_arch/aarch64/cpu.rs b/13_integrated_testing/src/_arch/aarch64/cpu.rs
index e7fe1711..7d146d23 100644
--- a/13_integrated_testing/src/_arch/aarch64/cpu.rs
+++ b/13_integrated_testing/src/_arch/aarch64/cpu.rs
@@ -80,14 +80,6 @@ unsafe fn el2_to_el1_transition() -> ! {
 
 pub use asm::nop;
 
-/// Spin for `n` cycles.
-#[inline(always)]
-pub fn spin_for_cycles(n: usize) {
-    for _ in 0..n {
-        asm::nop();
-    }
-}
-
 /// Pause execution on the core.
 #[inline(always)]
 pub fn wait_forever() -> ! {
diff --git a/13_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs b/13_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
index 0b01db4b..e06cbc7f 100644
--- a/13_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
+++ b/13_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
@@ -5,7 +5,7 @@
 //! GPIO Driver.
 
 use crate::{
-    bsp::device_driver::common::MMIODerefWrapper, cpu, driver, synchronization,
+    bsp::device_driver::common::MMIODerefWrapper, driver, synchronization,
     synchronization::NullLock,
 };
 use register::{mmio::*, register_bitfields, register_structs};
@@ -17,7 +17,8 @@ use register::{mmio::*, register_bitfields, register_structs};
 // GPIO registers.
 //
 // Descriptions taken from
-// https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
+// - https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
+// - https://datasheets.raspberrypi.org/bcm2711/bcm2711-peripherals.pdf
 register_bitfields! {
     u32,
 
@@ -39,7 +40,21 @@ register_bitfields! {
         ]
     ],
 
+    /// GPIO Pull-up/down Register
+    ///
+    /// BCM2837 only.
+    GPPUD [
+        /// Controls the actuation of the internal pull-up/down control line to ALL the GPIO pins.
+        PUD OFFSET(0) NUMBITS(2) [
+            Off = 0b00,
+            PullDown = 0b01,
+            PullUp = 0b10
+        ]
+    ],
+
     /// GPIO Pull-up/down Clock Register 0
+    ///
+    /// BCM2837 only.
     GPPUDCLK0 [
         /// Pin 15
         PUDCLK15 OFFSET(15) NUMBITS(1) [
@@ -52,23 +67,37 @@ register_bitfields! {
             NoEffect = 0,
             AssertClock = 1
         ]
+    ],
+
+    /// GPIO Pull-up / Pull-down Register 0
+    ///
+    /// BCM2711 only.
+    GPIO_PUP_PDN_CNTRL_REG0 [
+        /// Pin 15
+        GPIO_PUP_PDN_CNTRL15 OFFSET(30) NUMBITS(2) [
+            NoResistor = 0b00,
+            PullUp = 0b01
+        ],
+
+        /// Pin 14
+        GPIO_PUP_PDN_CNTRL14 OFFSET(28) NUMBITS(2) [
+            NoResistor = 0b00,
+            PullUp = 0b01
+        ]
     ]
 }
 
 register_structs! {
     #[allow(non_snake_case)]
     RegisterBlock {
-        (0x00 => GPFSEL0: ReadWrite<u32>),
+        (0x00 => _reserved1),
         (0x04 => GPFSEL1: ReadWrite<u32, GPFSEL1::Register>),
-        (0x08 => GPFSEL2: ReadWrite<u32>),
-        (0x0C => GPFSEL3: ReadWrite<u32>),
-        (0x10 => GPFSEL4: ReadWrite<u32>),
-        (0x14 => GPFSEL5: ReadWrite<u32>),
-        (0x18 => _reserved1),
-        (0x94 => GPPUD: ReadWrite<u32>),
+        (0x08 => _reserved2),
+        (0x94 => GPPUD: ReadWrite<u32, GPPUD::Register>),
         (0x98 => GPPUDCLK0: ReadWrite<u32, GPPUDCLK0::Register>),
-        (0x9C => GPPUDCLK1: ReadWrite<u32>),
-        (0xA0 => @END),
+        (0x9C => _reserved3),
+        (0xE4 => GPIO_PUP_PDN_CNTRL_REG0: ReadWrite<u32, GPIO_PUP_PDN_CNTRL_REG0::Register>),
+        (0xE8 => @END),
     }
 }
 
@@ -107,26 +136,52 @@ impl GPIOInner {
         }
     }
 
+    /// Disable pull-up/down on pins 14 and 15.
+    #[cfg(feature = "bsp_rpi3")]
+    fn disable_pud_14_15_bcm2837(&mut self) {
+        use crate::{time, time::interface::TimeManager};
+        use core::time::Duration;
+
+        // The Linux 2837 GPIO driver waits 1 µs between the steps.
+        const DELAY: Duration = Duration::from_micros(1);
+
+        self.registers.GPPUD.write(GPPUD::PUD::Off);
+        time::time_manager().spin_for(DELAY);
+
+        self.registers
+            .GPPUDCLK0
+            .write(GPPUDCLK0::PUDCLK15::AssertClock + GPPUDCLK0::PUDCLK14::AssertClock);
+        time::time_manager().spin_for(DELAY);
+
+        self.registers.GPPUD.write(GPPUD::PUD::Off);
+        self.registers.GPPUDCLK0.set(0);
+    }
+
+    /// Disable pull-up/down on pins 14 and 15.
+    #[cfg(feature = "bsp_rpi4")]
+    fn disable_pud_14_15_bcm2711(&mut self) {
+        self.registers.GPIO_PUP_PDN_CNTRL_REG0.write(
+            GPIO_PUP_PDN_CNTRL_REG0::GPIO_PUP_PDN_CNTRL15::PullUp
+                + GPIO_PUP_PDN_CNTRL_REG0::GPIO_PUP_PDN_CNTRL14::PullUp,
+        );
+    }
+
     /// Map PL011 UART as standard output.
     ///
     /// TX to pin 14
     /// RX to pin 15
     pub fn map_pl011_uart(&mut self) {
-        // Map to pins.
+        // Select the UART on pins 14 and 15.
         self.registers
             .GPFSEL1
-            .modify(GPFSEL1::FSEL14::AltFunc0 + GPFSEL1::FSEL15::AltFunc0);
+            .modify(GPFSEL1::FSEL15::AltFunc0 + GPFSEL1::FSEL14::AltFunc0);
 
-        // Enable pins 14 and 15.
-        self.registers.GPPUD.set(0);
-        cpu::spin_for_cycles(150);
+        // Disable pull-up/down on pins 14 and 15.
+        #[cfg(feature = "bsp_rpi3")]
+        self.disable_pud_14_15_bcm2837();
 
-        self.registers
-            .GPPUDCLK0
-            .write(GPPUDCLK0::PUDCLK14::AssertClock + GPPUDCLK0::PUDCLK15::AssertClock);
-        cpu::spin_for_cycles(150);
-
-        self.registers.GPPUDCLK0.set(0);
+        #[cfg(feature = "bsp_rpi4")]
+        self.disable_pud_14_15_bcm2711();
     }
 }
 
diff --git a/14_exceptions_part2_peripheral_IRQs/README.md b/14_exceptions_part2_peripheral_IRQs/README.md
index d15542d8..23f50fcd 100644
--- a/14_exceptions_part2_peripheral_IRQs/README.md
+++ b/14_exceptions_part2_peripheral_IRQs/README.md
@@ -1462,13 +1462,13 @@ diff -uNr 13_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 14_exc
 @@ -6,7 +6,7 @@
 
  use crate::{
-     bsp::device_driver::common::MMIODerefWrapper, cpu, driver, synchronization,
+     bsp::device_driver::common::MMIODerefWrapper, driver, synchronization,
 -    synchronization::NullLock,
 +    synchronization::IRQSafeNullLock,
  };
  use register::{mmio::*, register_bitfields, register_structs};
 
-@@ -88,7 +88,7 @@
+@@ -117,7 +117,7 @@
 
  /// Representation of the GPIO HW.
  pub struct GPIO {
@@ -1477,7 +1477,7 @@ diff -uNr 13_integrated_testing/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 14_exc
  }
 
  //--------------------------------------------------------------------------------------------------
-@@ -138,7 +138,7 @@
+@@ -193,7 +193,7 @@
      /// - The user must ensure to provide a correct MMIO start address.
      pub const unsafe fn new(mmio_start_addr: usize) -> Self {
          Self {
diff --git a/14_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/cpu.rs b/14_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/cpu.rs
index e7fe1711..7d146d23 100644
--- a/14_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/cpu.rs
+++ b/14_exceptions_part2_peripheral_IRQs/src/_arch/aarch64/cpu.rs
@@ -80,14 +80,6 @@ unsafe fn el2_to_el1_transition() -> ! {
 
 pub use asm::nop;
 
-/// Spin for `n` cycles.
-#[inline(always)]
-pub fn spin_for_cycles(n: usize) {
-    for _ in 0..n {
-        asm::nop();
-    }
-}
-
 /// Pause execution on the core.
 #[inline(always)]
 pub fn wait_forever() -> ! {
diff --git a/14_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs b/14_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
index 761dea0b..54b7133f 100644
--- a/14_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
+++ b/14_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
@@ -5,7 +5,7 @@
 //! GPIO Driver.
 
 use crate::{
-    bsp::device_driver::common::MMIODerefWrapper, cpu, driver, synchronization,
+    bsp::device_driver::common::MMIODerefWrapper, driver, synchronization,
     synchronization::IRQSafeNullLock,
 };
 use register::{mmio::*, register_bitfields, register_structs};
@@ -17,7 +17,8 @@ use register::{mmio::*, register_bitfields, register_structs};
 // GPIO registers.
 //
 // Descriptions taken from
-// https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
+// - https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
+// - https://datasheets.raspberrypi.org/bcm2711/bcm2711-peripherals.pdf
 register_bitfields! {
     u32,
 
@@ -39,7 +40,21 @@ register_bitfields! {
         ]
     ],
 
+    /// GPIO Pull-up/down Register
+    ///
+    /// BCM2837 only.
+    GPPUD [
+        /// Controls the actuation of the internal pull-up/down control line to ALL the GPIO pins.
+        PUD OFFSET(0) NUMBITS(2) [
+            Off = 0b00,
+            PullDown = 0b01,
+            PullUp = 0b10
+        ]
+    ],
+
     /// GPIO Pull-up/down Clock Register 0
+    ///
+    /// BCM2837 only.
     GPPUDCLK0 [
         /// Pin 15
         PUDCLK15 OFFSET(15) NUMBITS(1) [
@@ -52,23 +67,37 @@ register_bitfields! {
             NoEffect = 0,
             AssertClock = 1
         ]
+    ],
+
+    /// GPIO Pull-up / Pull-down Register 0
+    ///
+    /// BCM2711 only.
+    GPIO_PUP_PDN_CNTRL_REG0 [
+        /// Pin 15
+        GPIO_PUP_PDN_CNTRL15 OFFSET(30) NUMBITS(2) [
+            NoResistor = 0b00,
+            PullUp = 0b01
+        ],
+
+        /// Pin 14
+        GPIO_PUP_PDN_CNTRL14 OFFSET(28) NUMBITS(2) [
+            NoResistor = 0b00,
+            PullUp = 0b01
+        ]
     ]
 }
 
 register_structs! {
     #[allow(non_snake_case)]
     RegisterBlock {
-        (0x00 => GPFSEL0: ReadWrite<u32>),
+        (0x00 => _reserved1),
         (0x04 => GPFSEL1: ReadWrite<u32, GPFSEL1::Register>),
-        (0x08 => GPFSEL2: ReadWrite<u32>),
-        (0x0C => GPFSEL3: ReadWrite<u32>),
-        (0x10 => GPFSEL4: ReadWrite<u32>),
-        (0x14 => GPFSEL5: ReadWrite<u32>),
-        (0x18 => _reserved1),
-        (0x94 => GPPUD: ReadWrite<u32>),
+        (0x08 => _reserved2),
+        (0x94 => GPPUD: ReadWrite<u32, GPPUD::Register>),
         (0x98 => GPPUDCLK0: ReadWrite<u32, GPPUDCLK0::Register>),
-        (0x9C => GPPUDCLK1: ReadWrite<u32>),
-        (0xA0 => @END),
+        (0x9C => _reserved3),
+        (0xE4 => GPIO_PUP_PDN_CNTRL_REG0: ReadWrite<u32, GPIO_PUP_PDN_CNTRL_REG0::Register>),
+        (0xE8 => @END),
     }
 }
 
@@ -107,26 +136,52 @@ impl GPIOInner {
         }
     }
 
+    /// Disable pull-up/down on pins 14 and 15.
+    #[cfg(feature = "bsp_rpi3")]
+    fn disable_pud_14_15_bcm2837(&mut self) {
+        use crate::{time, time::interface::TimeManager};
+        use core::time::Duration;
+
+        // The Linux 2837 GPIO driver waits 1 µs between the steps.
+        const DELAY: Duration = Duration::from_micros(1);
+
+        self.registers.GPPUD.write(GPPUD::PUD::Off);
+        time::time_manager().spin_for(DELAY);
+
+        self.registers
+            .GPPUDCLK0
+            .write(GPPUDCLK0::PUDCLK15::AssertClock + GPPUDCLK0::PUDCLK14::AssertClock);
+        time::time_manager().spin_for(DELAY);
+
+        self.registers.GPPUD.write(GPPUD::PUD::Off);
+        self.registers.GPPUDCLK0.set(0);
+    }
+
+    /// Disable pull-up/down on pins 14 and 15.
+    #[cfg(feature = "bsp_rpi4")]
+    fn disable_pud_14_15_bcm2711(&mut self) {
+        self.registers.GPIO_PUP_PDN_CNTRL_REG0.write(
+            GPIO_PUP_PDN_CNTRL_REG0::GPIO_PUP_PDN_CNTRL15::PullUp
+                + GPIO_PUP_PDN_CNTRL_REG0::GPIO_PUP_PDN_CNTRL14::PullUp,
+        );
+    }
+
     /// Map PL011 UART as standard output.
     ///
     /// TX to pin 14
     /// RX to pin 15
     pub fn map_pl011_uart(&mut self) {
-        // Map to pins.
+        // Select the UART on pins 14 and 15.
         self.registers
             .GPFSEL1
-            .modify(GPFSEL1::FSEL14::AltFunc0 + GPFSEL1::FSEL15::AltFunc0);
+            .modify(GPFSEL1::FSEL15::AltFunc0 + GPFSEL1::FSEL14::AltFunc0);
 
-        // Enable pins 14 and 15.
-        self.registers.GPPUD.set(0);
-        cpu::spin_for_cycles(150);
+        // Disable pull-up/down on pins 14 and 15.
+        #[cfg(feature = "bsp_rpi3")]
+        self.disable_pud_14_15_bcm2837();
 
-        self.registers
-            .GPPUDCLK0
-            .write(GPPUDCLK0::PUDCLK14::AssertClock + GPPUDCLK0::PUDCLK15::AssertClock);
-        cpu::spin_for_cycles(150);
-
-        self.registers.GPPUDCLK0.set(0);
+        #[cfg(feature = "bsp_rpi4")]
+        self.disable_pud_14_15_bcm2711();
     }
 }
 
diff --git a/15_virtual_mem_part2_mmio_remap/README.md b/15_virtual_mem_part2_mmio_remap/README.md
index 0b60f8c5..e82c93ac 100644
--- a/15_virtual_mem_part2_mmio_remap/README.md
+++ b/15_virtual_mem_part2_mmio_remap/README.md
@@ -1052,16 +1052,16 @@ diff -uNr 14_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
  //! GPIO Driver.
 
  use crate::{
--    bsp::device_driver::common::MMIODerefWrapper, cpu, driver, synchronization,
+-    bsp::device_driver::common::MMIODerefWrapper, driver, synchronization,
 -    synchronization::IRQSafeNullLock,
-+    bsp::device_driver::common::MMIODerefWrapper, cpu, driver, memory, memory::mmu::Physical,
++    bsp::device_driver::common::MMIODerefWrapper, driver, memory, memory::mmu::Physical,
 +    synchronization, synchronization::IRQSafeNullLock,
  };
 +use core::sync::atomic::{AtomicUsize, Ordering};
  use register::{mmio::*, register_bitfields, register_structs};
 
  //--------------------------------------------------------------------------------------------------
-@@ -88,6 +89,8 @@
+@@ -117,6 +118,8 @@
 
  /// Representation of the GPIO HW.
  pub struct GPIO {
@@ -1070,7 +1070,7 @@ diff -uNr 14_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
      inner: IRQSafeNullLock<GPIOInner>,
  }
 
-@@ -107,6 +110,19 @@
+@@ -136,6 +139,19 @@
          }
      }
 
@@ -1087,10 +1087,10 @@ diff -uNr 14_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
 +        Ok(())
 +    }
 +
-     /// Map PL011 UART as standard output.
-     ///
-     /// TX to pin 14
-@@ -135,10 +151,14 @@
+     /// Disable pull-up/down on pins 14 and 15.
+     #[cfg(feature = "bsp_rpi3")]
+     fn disable_pud_14_15_bcm2837(&mut self) {
+@@ -190,10 +206,14 @@
      ///
      /// # Safety
      ///
@@ -1108,7 +1108,7 @@ diff -uNr 14_exceptions_part2_peripheral_IRQs/src/bsp/device_driver/bcm/bcm2xxx_
          }
      }
 
-@@ -158,4 +178,27 @@
+@@ -213,4 +233,27 @@
      fn compatible(&self) -> &'static str {
          "BCM GPIO"
      }
diff --git a/15_virtual_mem_part2_mmio_remap/src/_arch/aarch64/cpu.rs b/15_virtual_mem_part2_mmio_remap/src/_arch/aarch64/cpu.rs
index 59840838..c68f1817 100644
--- a/15_virtual_mem_part2_mmio_remap/src/_arch/aarch64/cpu.rs
+++ b/15_virtual_mem_part2_mmio_remap/src/_arch/aarch64/cpu.rs
@@ -80,14 +80,6 @@ unsafe fn el2_to_el1_transition() -> ! {
 
 pub use asm::nop;
 
-/// Spin for `n` cycles.
-#[inline(always)]
-pub fn spin_for_cycles(n: usize) {
-    for _ in 0..n {
-        asm::nop();
-    }
-}
-
 /// Pause execution on the core.
 #[inline(always)]
 pub fn wait_forever() -> ! {
diff --git a/15_virtual_mem_part2_mmio_remap/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs b/15_virtual_mem_part2_mmio_remap/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
index b9fc3c8b..e5fb0439 100644
--- a/15_virtual_mem_part2_mmio_remap/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
+++ b/15_virtual_mem_part2_mmio_remap/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
@@ -5,7 +5,7 @@
 //! GPIO Driver.
 
 use crate::{
-    bsp::device_driver::common::MMIODerefWrapper, cpu, driver, memory, memory::mmu::Physical,
+    bsp::device_driver::common::MMIODerefWrapper, driver, memory, memory::mmu::Physical,
     synchronization, synchronization::IRQSafeNullLock,
 };
 use core::sync::atomic::{AtomicUsize, Ordering};
@@ -18,7 +18,8 @@ use register::{mmio::*, register_bitfields, register_structs};
 // GPIO registers.
 //
 // Descriptions taken from
-// https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
+// - https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
+// - https://datasheets.raspberrypi.org/bcm2711/bcm2711-peripherals.pdf
 register_bitfields! {
     u32,
 
@@ -40,7 +41,21 @@ register_bitfields! {
         ]
     ],
 
+    /// GPIO Pull-up/down Register
+    ///
+    /// BCM2837 only.
+    GPPUD [
+        /// Controls the actuation of the internal pull-up/down control line to ALL the GPIO pins.
+        PUD OFFSET(0) NUMBITS(2) [
+            Off = 0b00,
+            PullDown = 0b01,
+            PullUp = 0b10
+        ]
+    ],
+
     /// GPIO Pull-up/down Clock Register 0
+    ///
+    /// BCM2837 only.
     GPPUDCLK0 [
         /// Pin 15
         PUDCLK15 OFFSET(15) NUMBITS(1) [
@@ -53,23 +68,37 @@ register_bitfields! {
             NoEffect = 0,
             AssertClock = 1
         ]
+    ],
+
+    /// GPIO Pull-up / Pull-down Register 0
+    ///
+    /// BCM2711 only.
+    GPIO_PUP_PDN_CNTRL_REG0 [
+        /// Pin 15
+        GPIO_PUP_PDN_CNTRL15 OFFSET(30) NUMBITS(2) [
+            NoResistor = 0b00,
+            PullUp = 0b01
+        ],
+
+        /// Pin 14
+        GPIO_PUP_PDN_CNTRL14 OFFSET(28) NUMBITS(2) [
+            NoResistor = 0b00,
+            PullUp = 0b01
+        ]
     ]
 }
 
 register_structs! {
     #[allow(non_snake_case)]
     RegisterBlock {
-        (0x00 => GPFSEL0: ReadWrite<u32>),
+        (0x00 => _reserved1),
         (0x04 => GPFSEL1: ReadWrite<u32, GPFSEL1::Register>),
-        (0x08 => GPFSEL2: ReadWrite<u32>),
-        (0x0C => GPFSEL3: ReadWrite<u32>),
-        (0x10 => GPFSEL4: ReadWrite<u32>),
-        (0x14 => GPFSEL5: ReadWrite<u32>),
-        (0x18 => _reserved1),
-        (0x94 => GPPUD: ReadWrite<u32>),
+        (0x08 => _reserved2),
+        (0x94 => GPPUD: ReadWrite<u32, GPPUD::Register>),
         (0x98 => GPPUDCLK0: ReadWrite<u32, GPPUDCLK0::Register>),
-        (0x9C => GPPUDCLK1: ReadWrite<u32>),
-        (0xA0 => @END),
+        (0x9C => _reserved3),
+        (0xE4 => GPIO_PUP_PDN_CNTRL_REG0: ReadWrite<u32, GPIO_PUP_PDN_CNTRL_REG0::Register>),
+        (0xE8 => @END),
     }
 }
 
@@ -123,26 +152,52 @@ impl GPIOInner {
         Ok(())
     }
 
+    /// Disable pull-up/down on pins 14 and 15.
+    #[cfg(feature = "bsp_rpi3")]
+    fn disable_pud_14_15_bcm2837(&mut self) {
+        use crate::{time, time::interface::TimeManager};
+        use core::time::Duration;
+
+        // The Linux 2837 GPIO driver waits 1 µs between the steps.
+        const DELAY: Duration = Duration::from_micros(1);
+
+        self.registers.GPPUD.write(GPPUD::PUD::Off);
+        time::time_manager().spin_for(DELAY);
+
+        self.registers
+            .GPPUDCLK0
+            .write(GPPUDCLK0::PUDCLK15::AssertClock + GPPUDCLK0::PUDCLK14::AssertClock);
+        time::time_manager().spin_for(DELAY);
+
+        self.registers.GPPUD.write(GPPUD::PUD::Off);
+        self.registers.GPPUDCLK0.set(0);
+    }
+
+    /// Disable pull-up/down on pins 14 and 15.
+    #[cfg(feature = "bsp_rpi4")]
+    fn disable_pud_14_15_bcm2711(&mut self) {
+        self.registers.GPIO_PUP_PDN_CNTRL_REG0.write(
+            GPIO_PUP_PDN_CNTRL_REG0::GPIO_PUP_PDN_CNTRL15::PullUp
+                + GPIO_PUP_PDN_CNTRL_REG0::GPIO_PUP_PDN_CNTRL14::PullUp,
+        );
+    }
+
     /// Map PL011 UART as standard output.
     ///
     /// TX to pin 14
     /// RX to pin 15
     pub fn map_pl011_uart(&mut self) {
-        // Map to pins.
+        // Select the UART on pins 14 and 15.
         self.registers
             .GPFSEL1
-            .modify(GPFSEL1::FSEL14::AltFunc0 + GPFSEL1::FSEL15::AltFunc0);
+            .modify(GPFSEL1::FSEL15::AltFunc0 + GPFSEL1::FSEL14::AltFunc0);
 
-        // Enable pins 14 and 15.
-        self.registers.GPPUD.set(0);
-        cpu::spin_for_cycles(150);
+        // Disable pull-up/down on pins 14 and 15.
+        #[cfg(feature = "bsp_rpi3")]
+        self.disable_pud_14_15_bcm2837();
 
-        self.registers
-            .GPPUDCLK0
-            .write(GPPUDCLK0::PUDCLK14::AssertClock + GPPUDCLK0::PUDCLK15::AssertClock);
-        cpu::spin_for_cycles(150);
-
-        self.registers.GPPUDCLK0.set(0);
+        #[cfg(feature = "bsp_rpi4")]
+        self.disable_pud_14_15_bcm2711();
     }
 }
 
diff --git a/X1_JTAG_boot/jtag_boot_rpi3.img b/X1_JTAG_boot/jtag_boot_rpi3.img
index 086b01aeab0f5ed1e855dda06b628d2d5fe8b165..88b5a6b4081da46555c0b7b6f678fb7fe82541f7 100755
GIT binary patch
delta 2917
zcmb7GZ%kX)6~FI28^33hga#7`2K<caYLkW}%>s-pi6QC+?mAK@8)(%OJeq-l05VkD
zq*`{ePD<8n%FQK78%q-;o$w`%LJM8ud}tv^TcW9zvn<)4PcJmmY#f3{qP5lpZ|B<2
zD`d@wJ?Z+rbI-Zwp5O2Mfxp%bf9qt4`#Oh)WF-Gto#AhZu6I1k`%$WKVASt?Lkw5G
zaU<-gFTdEtS+7Z)G$x5?Qc`x_sSMl*tAa797|;O`WG5`gdU8}(5iG|G7dV`Y&^QOn
zA>BA9Ary1ka`B1j61;Y)>Gr}F1N|iMNqC{1!wCaQtpz)}^wRD52_8E}jFzrz$35=c
z^Zrk#x8eEiBK;K#c}#(^@WOV9<_1EZL=8%HFa7xT!z&!^3K+wOV`0zX_K4pHcJ3f3
zY;8NR`%<pO1dh9>U%+DEQdqGgJll@2xa7Z`9OY?phQsm8C_48liY7+|I?tn_kcf6H
z?{}qu2|Ohnyz2~zVa5n!V-F`LuZ!q_5qu`tMY}fPxlu&ZYykQu2~E1eJ_u-Hp90$S
z<s;>I9#A$(H_tIf9zx`dh55@IO#<2~U<VwYbU#yt=OMra!r|nEKyUn3wD^F9CSYOy
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zD<hk6yaPp#frAG%2ATi{62OWADVqgG=IkO(*d;m!Y)pNwejUL%0hSIHl526hQj5L%
zkmt?eZ{XPrJbnf2SnU|6et*h6@Q=kkT+o<Ia2c9zGMb)UO_TJw`XO`5Glx@^*d~NL
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zf~VNtvS~&B-mlQ{1^e`9h;gNShA^XGRzUdC#4g^!@p3ik5MBwgR4=!DL<=BukDEFA
zOI^rgh7<X~?9g>5jvTE|DS~<Io?soD74j=3y(`*OVBRk2QIzSdr%|+dSv||XCG@su
zmF+ty+NkN6ofYKA&GmG-<$8qO3#;v}2p6*^5s&0zCoEQL5|9W)#ek?7Y7?**f@)~f
z;cZ&Crkje{{sMi$>~E^-0kF+<@?QSd<7SaE5JTr{$R7kxGgR0dAXf}Il(AuxcVcBP
z!tv*Hv=Q<&_ne-B%W<c-4y!>Pih!dD0s7M}P+7Z@<qZwj;Pa|_mUQZNmqM%0pr^Gu
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z9<WdMuL22UNz;hFs{${}Ed~nQ1nF<!P@4fwo(A-Q{A9uXQGeWyu=Agr@z~-Xtg3vP
zK;;6WtP&CzIeHwD5aC@>RuwC=?0{;B@F@E6DHQ$nl6qErq6#8spyk+p&QTAA0LA;k
zQ9m>O7!;KdfN3rC<IfScawy8uV=X{YR;*IJ^{TTi<S`zxUS$Prnzmkr%80U*u?m=j
zf#ST!<G8A$@x2H?fJvra(9>C9Wf%Y|IbSl&fHF`F=<y&!0w`D3c@|MTAEj8GGo&k#
zwLS%zXBD#l1(pT`L8k#~z=ErgLF8FvtQSNtj~|#&N)761e3Oo*_eKC^Fei<yi={4=
zo=!2Six^C&7?Kf8CzP2^Q!vedfoJ|(7p~OH2${tS7dt<u2%-dqA&t%Q$V^(rssd+v
zT*Ksy%|R^P_Z;|yO;2F>=fxC*K;tt|7eJqz)03pQX-zpZkFkF0<_yFxZ7t69FQ>=O
z5j`~3M^rIzQ~`q;a#)(?swTD=C%L>>gKWYOv6*#sL&!Ao$W+bow{%2ZQ%V}we8^Ah
zCe$@0dU4#Xcb)3Krz7_KxNh8e#4xeWyp_uxui#8?y~vsV*nsrprGnbDimWrACM6rf
ztF<#5Ds<yE#YB=DUL@niGS^RT71suT<m>1-<R3Wf?ddt>f3-!f`k}nP-`6X@_PXCY
z=<Dm1<-tyGuk7`=clrhowGYB}PtVWff!F){`}~84UVC01==Sx)i4ORag3#S!$PGMz
zDgFFSlOg5lr(csb5pDdtwvngp%xQ8ZsV}<B3FJsoA=y`y7nC)9*71{J4)*oQJ$=0$
zPsH<o2h>=S0btKYn0b@tqLE;pkkMs+5z4-6^_efTrbn9Gu=izo-*>id+a`an-UGw?
z-JGvJ-wFRkvFE4SJ8M^zxjTE$Ce)}oXw}}xo;mn-speRdr%K5WHdZ&vhRn9+24#~V
zYa9>w+qd-leZ7NK{sCswT9&bgvQIzj;de7E(py-xKBOr(WOV3E897&2#$PQX*9yP;
zf}&}&>G@2Pvsd2NWbH7zUq<SRekU@9zP+!hnY3-(TKA>~KWmdcyDD67udn^!PrSZt
z%wXIqlZN82@yBG+Ra_=V<P3;)nwu+{ob^T|i;MraOgxsVI+txVL0K8PG5rjiR_n7q
q-ZhbHmfh=*X~$*FJYplpl7AIP$}^`d+I9<!BbYoWQcj9XcmD@5w|7qf

delta 1828
zcmbtVO>7%Q6rS1jI_ubNeu(4LcI;h}H2$fblq4mjC~+O7Kom&X27yGS#BzHGi9$(=
zsJPfEMHICM50i@03Mml>x)oK8+)DKYIqHSNg+d!uLPG1nAr6tC0wKZy^JaIQ5~&9y
zo-{l2e&)UR&3jL~c<_E-#w)&!(Sn4eySZB4!a4T~XaOUX)qX@oE_lf*kH`<Xpb)@Z
zx|trfzF1Qp<nH`FDyj`&wZOH}cdC@pC5fzqp;l#8*=1St5p58WwRVg8EJ`cu?Sg6p
zc~JI|a*9(+Em$q_n3P(0b-)adK#x!xIgHQ(Z58{Qo#dBWh&VvZTn21kUesOS9&&EE
zhNi?QCrk92xNj$9IegXOv4ho=EYsgaIpqSUF^qb~CH`KyTy`<%94u4_6PZsd@mQFw
zKp=*j>3CQcrcbw#WNbG{2x;XsY6tX~+%WA5{P>CpHfJqq#rE;R&5#hwzvgV{3JEBG
zyFRUmAoHI`dB4P`?ga((V7Xi#t40?TrmX%*S8U1sz%z#xrwp2y=pjK^16cgohSAto
z(ye<)0)ob45u%#O=ug3H-$j2i``Zxf)pGem2B^TN##hR>@SVTA(B>t$a0W^s{`BeW
zq7_}QMkrH)QVq{b#QtDFFNfBS)b}C4dIwgkaV#GKRC>}Fk|x^|-vVSH-2!B@o>CZk
z8^pPs!f7Q0LG3%!%0?0qRzRq8o;B2f6Xmr}FbN#+-waHE-Ms&1cp1*1XQ)`e1mzIf
zcoJ=vQx@nIUR`T}UJ489Dm26rdjadi(%MWAr5d!!KrjHQ|Bc{Z09f)2#5Mqs(4zpb
z{t%af3fZVKvR@1HsxB-B$y&-l@CHNhSGjvz<4v@aq!ch4FGv{DCbQNE#Wu(2y!|n$
z#37hE7zjuYErtl|9*y^3DZ*lBdchubdI_5ZHaF{oh)fkd<Q$ID@9nYLtX2hY37&)S
z#>2%34Lia+oVq!i-l<{-O*%T=Syl$I7$L#=D2(tIs#b+n4Gi|vtBz$X=U(4&9oJ^#
zsGGptG_bjfPju(HYW897^9UWNYo=#vZ*WVI+(4aI5HrI<?1QQ02u(JwSu(*yXKvKh
zi5;0%Y(G1M?O(^W2tC`>tE=d!>pVTO>(X{D?{2kZ<U%(MyNCK)5xggm@qM_DaE2sc
zY8p&FKKQ(JXry!RUg@O+${0=in&1g%T!wL@?h2vPE_%i1<1V}CSH2gX`o`1(I-R~V
zdFTY4?wY*Gq6+^6O?a-QJ`*0D;M1ZZA2Iie9h6xoLyOQ6-Z)L0dvCMB|Jr2iF_UlF
zW$?+w^z^Z#(u8ts?#<~FebnWXhmh6KRWht(t~DC+x!GjL@!83l6Vcf@W|K92LD%S1
z58ntCd|iEG|HV^cW->YcR${W^4sHkBbXMBUz2c@9C12pA+lX6ZxJU1qd?hbdq-PF2
zH%gDYC7h+i-AnIFG3Y~`_IRjUj`p4OYzI~0p#gQ8Fdx=rQN{UDk)D$K>kH;}$<%8e
b`mOwjTk{%TJ*N0&_z%><S@Y7>$NT>Q9m?Ki

diff --git a/X1_JTAG_boot/jtag_boot_rpi4.img b/X1_JTAG_boot/jtag_boot_rpi4.img
index 1e3c185ba8502dcb400bb8c97b2cdd32a6f06e7a..5b4fc45d19dfdf9a7bab6b1c2cc47391b3e10f64 100755
GIT binary patch
delta 1208
zcmY*YUuauZ7(eIS+~(fQw$!vq?@gMUEN#;yGuztPVIOSlm}V8G+!kbG(v*VeCQ>@z
zb1RCg`mn=Sb&o3|?hZjqRFW5$(mm7{b)asbVB#3m6qG%!Sz*`j{z-=i?mc|x`+eW<
zcYgP~TN8Jlxg4c$t`AtWZ$Kogl#s6zHI>)z68@J!c&&Vt4N_)A;1%IKV@cQ)rk`Ak
z@$Hn)+{SzW@zaSYXuepe9_95Dgde12HBREc5KIx0gc+aCco4oo#Cj*+!Ny&f`H_zC
zZruM(#Nc;dh9xxci{mASnj$sj4+&Y#Q}Xm&T=><ptgzFsmgWqrrt)c?5DdMFn0+oI
z$py?U<OjJA_jk#V(`Q~Z^eY~&Cd~aNVNQPa`Bp~ES3mR_`uV=zv5ZKn5}uW0a$T42
zk*W=BgQfW~E@M#|_em=4$dt@FVg@swm@J>iMxS^j``Gu$u8se}vSweitWRyBc28@Q
z-g-1fT9*)iRV3foK4Q(~^m6PZw@S?XfEaq<=8Yv=T|G(6!u?79caoX~ny<c&YHg7P
zii$hl(Iv#4YLKc)4PC=Ct&ddU=Z+zk7=Z^JF~`u)(9li79TUXIhF(G%yWFN+L8<`K
zG`mSFfHWD8CV(viNMp;9k>(oGq_J)e&*zY;@SIkWx(xl)vQ{Z<XqAzo;YizFaA)Ji
z>9rK!_LEjKC78DJQX_?T#NjE4=KioHaoAAcqHW-wb<8ohIOKlK_^|giQ(*aX?CJ;{
zmZm~f<p;3a6ZkYw5Psp7!at&i;C<;dYh>ZJl<DF@2hkKT+jt7P<?-G|mZz5w;p~2I
z*8SA1W9l@Vk!x&5D@Ov~(JnG-bM`tDRvaz=d0?Ef^(^dk4#2U_Z`oS5ywiD5WE)xN
z4mR0*uDlnVpsb#S<9!nt!d~!WkV2o^CtrnzS#1<<ht_)j3E{<Yg`77bK3EBBbOg-s
zOGjT0yE&wF){GaUHO`v#VlO1KknaB}Q1QD}TYg|lPOU`UaIxRrYhHY%AEuRYx&_Nh
zSUKmZxVW@%cyZ~Cx8BYzU9`I%fpz5tCEDSZwt3q8=b%T`*fj-4)nRr=fwO9?XIF8t
z`1?A`4=d_%dIUDq68lnxsYq^OSN(sxc8tzC>ksb&UP#(>bw6B>Jlm6xxaDy#UxZfV
O0WHG)Xc*t}z~p~g6;k{F

delta 1292
zcmbtUU2GIp6h8OP{><=G(x2Vw>`!M_OSijZ7f4IB8$-8X5F4X*ZNiHYHavisC={X(
zJnUdFQEMXCLu2uU-57%tUN8&BeUU9~q9jDo2r=rzR(WWb2jEHTgX5XmS=7LrH<`IP
z_dECdzH{%H`Em5?+^HCQ{j<2uLZf~-%>XVW%$R8W2I5x<#4pvYyr1!W9QR0v_?3QK
zkS4l{hFDJetYyO2Q2xYH9Ccq`xZEciJ3(w`aM}Rl2OtRQ{rG~fz$Zg^jxvsH5VwiA
zgOG3Lhs6e(?=0!~voFn;3=H~5O0F~`X(qzNlV`APuOZ#AZCiEu%uRyRt{t#RBqXzN
z1OBCz-zX%)_QQbi(R{K#;PMpxX5pfjSC{tQlnGO2cde%V`Pz)nEF22;45j^0lWDD_
z&qD2Lms!wBH06hT^R_*uz+6E&^WeHpYYt(XR8DLY3X!L19%J%tg~60-`c~U?Mifc#
zQ_sx(+_&HlC;zH#m!@8{?GK&Pb4cw4_T67Yu=){gcpJ=uym)!K9Ds`}t%E-`F>Z)P
z5-jE3m}n-MWtX_6uzc-Z5_y`cA_FyDJZRi4=plvbvtc@hz?-g+?raW0&0=N&&A>*!
zl)`g?KKF(`rW;xSQFaOm{BuK&j}@DIsIdC~d_3HSGOmAtCj*IzVoEFrVYQi*Eax`m
zN=n!zYRHn`y5GQ$QUjC6!;Z&4?P2#KjAW}r8cDB12J!u1mhVgB<=~F+d{nF@wsrJ0
zcY=6DM8$ja8C2zGc_o7f<aEbm$jxX<gjP1=S$U+Vk`bx#EPW4OT8$vH8U#IoD{`H8
zC#vU_&sj%($kFU^yVe-4zP5IR@go^LzCMnN>n`zPrh0t+BYu7&gJ-*%Jh7!Z)170y
zoWZYpauniB_bkqZK5<sY!UNnK#slF>=SwOTP9yBT0gj=j>TC{2)#tX>J&a`CvEapY
zH11gRVlRY6tf}9w8I)U$kIVQ$Z#FU*Z-tHC*1W}wWetDo9btE|Q&Y8T;TCvwdjICb
z(=WezEIWPFVJ+jh_LTNypoO+|+WOb9qUpRhf>*QwzB__Vt*`T7q?Jp*1b4iFTI4ZS
z#>q&D$D;UsB%3=J{V!cRrjvEYGhP8+2yMCNWz0plcV6(e8y<cg---UtuH%WAO7AnV
GvA+STW_P{-

diff --git a/X1_JTAG_boot/src/_arch/aarch64/cpu.rs b/X1_JTAG_boot/src/_arch/aarch64/cpu.rs
index f2d96678..3f502ee0 100644
--- a/X1_JTAG_boot/src/_arch/aarch64/cpu.rs
+++ b/X1_JTAG_boot/src/_arch/aarch64/cpu.rs
@@ -20,7 +20,7 @@ use cortex_a::{asm, regs::*};
 /// - Linker script must ensure to place this function at `0x80_000`.
 #[naked]
 #[no_mangle]
-pub unsafe extern "C" fn _start() -> ! {
+pub unsafe fn _start() -> ! {
     use crate::runtime_init;
 
     // Expect the boot core to start in EL2.
@@ -39,14 +39,6 @@ pub unsafe extern "C" fn _start() -> ! {
 
 pub use asm::nop;
 
-/// Spin for `n` cycles.
-#[inline(always)]
-pub fn spin_for_cycles(n: usize) {
-    for _ in 0..n {
-        asm::nop();
-    }
-}
-
 /// Pause execution on the core.
 #[inline(always)]
 pub fn wait_forever() -> ! {
diff --git a/X1_JTAG_boot/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs b/X1_JTAG_boot/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
index 0b01db4b..e06cbc7f 100644
--- a/X1_JTAG_boot/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
+++ b/X1_JTAG_boot/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs
@@ -5,7 +5,7 @@
 //! GPIO Driver.
 
 use crate::{
-    bsp::device_driver::common::MMIODerefWrapper, cpu, driver, synchronization,
+    bsp::device_driver::common::MMIODerefWrapper, driver, synchronization,
     synchronization::NullLock,
 };
 use register::{mmio::*, register_bitfields, register_structs};
@@ -17,7 +17,8 @@ use register::{mmio::*, register_bitfields, register_structs};
 // GPIO registers.
 //
 // Descriptions taken from
-// https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
+// - https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
+// - https://datasheets.raspberrypi.org/bcm2711/bcm2711-peripherals.pdf
 register_bitfields! {
     u32,
 
@@ -39,7 +40,21 @@ register_bitfields! {
         ]
     ],
 
+    /// GPIO Pull-up/down Register
+    ///
+    /// BCM2837 only.
+    GPPUD [
+        /// Controls the actuation of the internal pull-up/down control line to ALL the GPIO pins.
+        PUD OFFSET(0) NUMBITS(2) [
+            Off = 0b00,
+            PullDown = 0b01,
+            PullUp = 0b10
+        ]
+    ],
+
     /// GPIO Pull-up/down Clock Register 0
+    ///
+    /// BCM2837 only.
     GPPUDCLK0 [
         /// Pin 15
         PUDCLK15 OFFSET(15) NUMBITS(1) [
@@ -52,23 +67,37 @@ register_bitfields! {
             NoEffect = 0,
             AssertClock = 1
         ]
+    ],
+
+    /// GPIO Pull-up / Pull-down Register 0
+    ///
+    /// BCM2711 only.
+    GPIO_PUP_PDN_CNTRL_REG0 [
+        /// Pin 15
+        GPIO_PUP_PDN_CNTRL15 OFFSET(30) NUMBITS(2) [
+            NoResistor = 0b00,
+            PullUp = 0b01
+        ],
+
+        /// Pin 14
+        GPIO_PUP_PDN_CNTRL14 OFFSET(28) NUMBITS(2) [
+            NoResistor = 0b00,
+            PullUp = 0b01
+        ]
     ]
 }
 
 register_structs! {
     #[allow(non_snake_case)]
     RegisterBlock {
-        (0x00 => GPFSEL0: ReadWrite<u32>),
+        (0x00 => _reserved1),
         (0x04 => GPFSEL1: ReadWrite<u32, GPFSEL1::Register>),
-        (0x08 => GPFSEL2: ReadWrite<u32>),
-        (0x0C => GPFSEL3: ReadWrite<u32>),
-        (0x10 => GPFSEL4: ReadWrite<u32>),
-        (0x14 => GPFSEL5: ReadWrite<u32>),
-        (0x18 => _reserved1),
-        (0x94 => GPPUD: ReadWrite<u32>),
+        (0x08 => _reserved2),
+        (0x94 => GPPUD: ReadWrite<u32, GPPUD::Register>),
         (0x98 => GPPUDCLK0: ReadWrite<u32, GPPUDCLK0::Register>),
-        (0x9C => GPPUDCLK1: ReadWrite<u32>),
-        (0xA0 => @END),
+        (0x9C => _reserved3),
+        (0xE4 => GPIO_PUP_PDN_CNTRL_REG0: ReadWrite<u32, GPIO_PUP_PDN_CNTRL_REG0::Register>),
+        (0xE8 => @END),
     }
 }
 
@@ -107,26 +136,52 @@ impl GPIOInner {
         }
     }
 
+    /// Disable pull-up/down on pins 14 and 15.
+    #[cfg(feature = "bsp_rpi3")]
+    fn disable_pud_14_15_bcm2837(&mut self) {
+        use crate::{time, time::interface::TimeManager};
+        use core::time::Duration;
+
+        // The Linux 2837 GPIO driver waits 1 µs between the steps.
+        const DELAY: Duration = Duration::from_micros(1);
+
+        self.registers.GPPUD.write(GPPUD::PUD::Off);
+        time::time_manager().spin_for(DELAY);
+
+        self.registers
+            .GPPUDCLK0
+            .write(GPPUDCLK0::PUDCLK15::AssertClock + GPPUDCLK0::PUDCLK14::AssertClock);
+        time::time_manager().spin_for(DELAY);
+
+        self.registers.GPPUD.write(GPPUD::PUD::Off);
+        self.registers.GPPUDCLK0.set(0);
+    }
+
+    /// Disable pull-up/down on pins 14 and 15.
+    #[cfg(feature = "bsp_rpi4")]
+    fn disable_pud_14_15_bcm2711(&mut self) {
+        self.registers.GPIO_PUP_PDN_CNTRL_REG0.write(
+            GPIO_PUP_PDN_CNTRL_REG0::GPIO_PUP_PDN_CNTRL15::PullUp
+                + GPIO_PUP_PDN_CNTRL_REG0::GPIO_PUP_PDN_CNTRL14::PullUp,
+        );
+    }
+
     /// Map PL011 UART as standard output.
     ///
     /// TX to pin 14
     /// RX to pin 15
     pub fn map_pl011_uart(&mut self) {
-        // Map to pins.
+        // Select the UART on pins 14 and 15.
         self.registers
             .GPFSEL1
-            .modify(GPFSEL1::FSEL14::AltFunc0 + GPFSEL1::FSEL15::AltFunc0);
+            .modify(GPFSEL1::FSEL15::AltFunc0 + GPFSEL1::FSEL14::AltFunc0);
 
-        // Enable pins 14 and 15.
-        self.registers.GPPUD.set(0);
-        cpu::spin_for_cycles(150);
+        // Disable pull-up/down on pins 14 and 15.
+        #[cfg(feature = "bsp_rpi3")]
+        self.disable_pud_14_15_bcm2837();
 
-        self.registers
-            .GPPUDCLK0
-            .write(GPPUDCLK0::PUDCLK14::AssertClock + GPPUDCLK0::PUDCLK15::AssertClock);
-        cpu::spin_for_cycles(150);
-
-        self.registers.GPPUDCLK0.set(0);
+        #[cfg(feature = "bsp_rpi4")]
+        self.disable_pud_14_15_bcm2711();
     }
 }