From 0f1f09730d2cbaa1f9f4fc1bd4fb701dfcc11622 Mon Sep 17 00:00:00 2001
From: Andre Richter <andre.o.richter@gmail.com>
Date: Mon, 4 Feb 2019 20:23:59 +0100
Subject: [PATCH] Align cache tutorial as well

---
 0D_cache_performance/kernel8     | Bin 71984 -> 71984 bytes
 0D_cache_performance/kernel8.img | Bin 3420 -> 3420 bytes
 0D_cache_performance/src/main.rs |   1 +
 0D_cache_performance/src/mmu.rs  |  47 +++++++++++++++++++++++--------
 4 files changed, 37 insertions(+), 11 deletions(-)

diff --git a/0D_cache_performance/kernel8 b/0D_cache_performance/kernel8
index f1bc1ae45156679df366a32738d48a7323b53891..673897fdfa11c1a14a717a3e5d7cb9a9b90fae88 100755
GIT binary patch
delta 41
wcmdn6iDknkmWC~iGK}Jv6gy_wGx5GwnB@O!BCEs2KqkReK(Xz{jEsN90Z-izuK)l5

delta 41
wcmdn6iDknkmWC~iGK}IvhJCZ_nRs6-O!EIVk=5a1Ad}!KpxAa}M#jJ505)k3TL1t6

diff --git a/0D_cache_performance/kernel8.img b/0D_cache_performance/kernel8.img
index 49bff063bff176d13770638126857cc12a50bfbc..06cee9298c40538b587c46a786465a9591182af7 100755
GIT binary patch
delta 36
rcmca3bw_H045RoZ#g19_OuVlZCi(xG$m(!0kV$YAP;9d?qb3gk1@{eR

delta 36
rcmca3bw_H045PS^Vc#r!Cf?Tyll*^8WOcY0$RxN5D7M*{QIiJ%?Z^xg

diff --git a/0D_cache_performance/src/main.rs b/0D_cache_performance/src/main.rs
index 94a88df4..0a02da69 100644
--- a/0D_cache_performance/src/main.rs
+++ b/0D_cache_performance/src/main.rs
@@ -24,6 +24,7 @@
 
 #![no_std]
 #![no_main]
+#![feature(range_contains)]
 
 const MMIO_BASE: u32 = 0x3F00_0000;
 
diff --git a/0D_cache_performance/src/mmu.rs b/0D_cache_performance/src/mmu.rs
index d3da12fd..6198bb02 100644
--- a/0D_cache_performance/src/mmu.rs
+++ b/0D_cache_performance/src/mmu.rs
@@ -99,8 +99,7 @@ static mut SINGLE_LVL3_TABLE: PageTable = PageTable {
     entries: [0; NUM_ENTRIES_4KIB],
 };
 
-/// Set up identity mapped page tables for the first 1 gigabyte of address
-/// space.
+/// Set up identity mapped page tables for the first 1 GiB of address space.
 pub unsafe fn init() {
     // First, define the three memory types that we will map. Cacheable and
     // non-cacheable normal DRAM, and device.
@@ -125,14 +124,27 @@ pub unsafe fn init() {
         pub const NORMAL_NON_CACHEABLE: u64 = 2;
     }
 
-    // Set up the first LVL2 entry, pointing to a 4KiB table base address.
+    // The first 2 MiB.
+    //
+    // Set up the first LVL2 entry, pointing to the base address of a follow-up
+    // table containing 4 KiB pages.
+    //
+    // 0x0000_0000_0000_0000 |
+    //                       |> 2 MiB
+    // 0x0000_0000_001F_FFFF |
     let lvl3_base: u64 = SINGLE_LVL3_TABLE.entries.base_addr() >> 12;
     LVL2_TABLE.entries[0] = (STAGE1_DESCRIPTOR::VALID::True
         + STAGE1_DESCRIPTOR::TYPE::Table
         + STAGE1_DESCRIPTOR::NEXT_LVL_TABLE_ADDR_4KiB.val(lvl3_base))
     .value;
 
-    // The second 2 MiB block.
+    // The second 2 MiB as block entry.
+    //
+    // Mapped as non-cacheable.
+    //
+    // 0x0000_0000_0020_0000 |
+    //                       |> 2 MiB
+    // 0x0000_0000_003F_FFFF |
     LVL2_TABLE.entries[1] = (STAGE1_DESCRIPTOR::VALID::True
         + STAGE1_DESCRIPTOR::TYPE::Block
         + STAGE1_DESCRIPTOR::AttrIndx.val(mair::NORMAL_NON_CACHEABLE)
@@ -148,9 +160,22 @@ pub unsafe fn init() {
         + STAGE1_DESCRIPTOR::XN::True)
         .value;
 
-    // Fill the rest of the LVL2 (2MiB) entries as block
-    // descriptors. Differentiate between normal and device mem.
-    let mmio_base: u64 = (super::MMIO_BASE >> 21).into();
+    // Fill the rest of the LVL2 (2 MiB) entries as block descriptors.
+    //
+    // Differentiate between
+    //   - cacheable DRAM
+    //   - device memory
+    //
+    // Ranges are stored in memory.rs.
+    //
+    // 0x0000_0000_0040_0000 |
+    //                       |> 1004 MiB cacheable DRAM
+    // 0x0000_0000_3EFF_FFFF |
+    // 0x0000_0000_3F00_0000 |
+    //                       |> 16 MiB device (MMIO)
+    // 0x0000_0000_4000_0000 |
+    let mmio_first_block_index: u64 = (super::MMIO_BASE >> 21).into();
+
     let common = STAGE1_DESCRIPTOR::VALID::True
         + STAGE1_DESCRIPTOR::TYPE::Block
         + STAGE1_DESCRIPTOR::AP::RW_EL1
@@ -162,7 +187,7 @@ pub unsafe fn init() {
     for (i, entry) in LVL2_TABLE.entries.iter_mut().enumerate().skip(2) {
         let j: u64 = i as u64;
 
-        let mem_attr = if j >= mmio_base {
+        let mem_attr = if j >= mmio_first_block_index {
             STAGE1_DESCRIPTOR::SH::OuterShareable + STAGE1_DESCRIPTOR::AttrIndx.val(mair::DEVICE)
         } else {
             STAGE1_DESCRIPTOR::SH::InnerShareable + STAGE1_DESCRIPTOR::AttrIndx.val(mair::NORMAL)
@@ -202,10 +227,10 @@ pub unsafe fn init() {
     for (i, entry) in SINGLE_LVL3_TABLE.entries.iter_mut().enumerate() {
         let j: u64 = i as u64;
 
-        let mem_attr = if j < ro_first_page_index || j > ro_last_page_index {
-            STAGE1_DESCRIPTOR::AP::RW_EL1 + STAGE1_DESCRIPTOR::XN::True
-        } else {
+        let mem_attr = if (ro_first_page_index..=ro_last_page_index).contains(&j) {
             STAGE1_DESCRIPTOR::AP::RO_EL1 + STAGE1_DESCRIPTOR::XN::False
+        } else {
+            STAGE1_DESCRIPTOR::AP::RW_EL1 + STAGE1_DESCRIPTOR::XN::True
         };
 
         *entry = (common + mem_attr + STAGE1_DESCRIPTOR::NEXT_LVL_TABLE_ADDR_4KiB.val(j)).value;