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404 lines
14 KiB
Rust
404 lines
14 KiB
Rust
5 years ago
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// SPDX-License-Identifier: MIT OR Apache-2.0
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//
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// Copyright (c) 2018-2021 Andre Richter <andre.o.richter@gmail.com>
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//! PL011 UART driver.
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//!
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//! # Resources
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//!
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//! - <https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf>
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//! - <https://developer.arm.com/documentation/ddi0183/latest>
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use crate::{
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bsp::device_driver::common::MMIODerefWrapper, console, cpu, driver, synchronization,
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synchronization::NullLock,
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};
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use core::fmt;
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use register::{mmio::*, register_bitfields, register_structs};
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//--------------------------------------------------------------------------------------------------
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// Private Definitions
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//--------------------------------------------------------------------------------------------------
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// PL011 UART registers.
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//
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// Descriptions taken from "PrimeCell UART (PL011) Technical Reference Manual" r1p5.
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register_bitfields! {
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u32,
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/// Flag Register.
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FR [
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/// Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
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/// Line Control Register, LCR_H.
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///
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/// - If the FIFO is disabled, this bit is set when the transmit holding register is empty.
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/// - If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty.
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/// - This bit does not indicate if there is data in the transmit shift register.
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TXFE OFFSET(7) NUMBITS(1) [],
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/// Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the
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/// LCR_H Register.
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///
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/// - If the FIFO is disabled, this bit is set when the transmit holding register is full.
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/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
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TXFF OFFSET(5) NUMBITS(1) [],
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/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
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/// LCR_H Register.
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///
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/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
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/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
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/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
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/// LCR_H Register.
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///
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/// - If the FIFO is disabled, this bit is set when the receive holding register is empty.
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/// - If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
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RXFE OFFSET(4) NUMBITS(1) [],
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/// UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains
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/// set until the complete byte, including all the stop bits, has been sent from the shift
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/// register.
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///
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/// This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether
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/// the UART is enabled or not.
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BUSY OFFSET(3) NUMBITS(1) []
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],
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/// Integer Baud Rate Divisor.
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IBRD [
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/// The integer baud rate divisor.
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BAUD_DIVINT OFFSET(0) NUMBITS(16) []
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],
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/// Fractional Baud Rate Divisor.
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FBRD [
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/// The fractional baud rate divisor.
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BAUD_DIVFRAC OFFSET(0) NUMBITS(6) []
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],
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/// Line Control Register.
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LCR_H [
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/// Word length. These bits indicate the number of data bits transmitted or received in a
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/// frame.
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WLEN OFFSET(5) NUMBITS(2) [
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FiveBit = 0b00,
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SixBit = 0b01,
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SevenBit = 0b10,
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EightBit = 0b11
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],
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/// Enable FIFOs:
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///
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/// 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding
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/// registers.
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///
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/// 1 = Transmit and receive FIFO buffers are enabled (FIFO mode).
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FEN OFFSET(4) NUMBITS(1) [
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FifosDisabled = 0,
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FifosEnabled = 1
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]
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],
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/// Control Register.
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CR [
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/// Receive enable. If this bit is set to 1, the receive section of the UART is enabled.
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/// Data reception occurs for either UART signals or SIR signals depending on the setting of
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/// the SIREN bit. When the UART is disabled in the middle of reception, it completes the
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/// current character before stopping.
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RXE OFFSET(9) NUMBITS(1) [
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Disabled = 0,
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Enabled = 1
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],
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/// Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled.
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/// Data transmission occurs for either UART signals, or SIR signals depending on the
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/// setting of the SIREN bit. When the UART is disabled in the middle of transmission, it
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/// completes the current character before stopping.
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TXE OFFSET(8) NUMBITS(1) [
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Disabled = 0,
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Enabled = 1
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],
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/// UART enable:
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///
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/// 0 = UART is disabled. If the UART is disabled in the middle of transmission or
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/// reception, it completes the current character before stopping.
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///
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/// 1 = The UART is enabled. Data transmission and reception occurs for either UART signals
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/// or SIR signals depending on the setting of the SIREN bit
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UARTEN OFFSET(0) NUMBITS(1) [
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/// If the UART is disabled in the middle of transmission or reception, it completes the
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/// current character before stopping.
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Disabled = 0,
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Enabled = 1
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]
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],
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/// Interrupt Clear Register.
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ICR [
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/// Meta field for all pending interrupts.
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ALL OFFSET(0) NUMBITS(11) []
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]
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}
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register_structs! {
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#[allow(non_snake_case)]
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pub RegisterBlock {
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(0x00 => DR: ReadWrite<u32>),
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(0x04 => _reserved1),
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(0x18 => FR: ReadOnly<u32, FR::Register>),
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(0x1c => _reserved2),
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(0x24 => IBRD: WriteOnly<u32, IBRD::Register>),
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(0x28 => FBRD: WriteOnly<u32, FBRD::Register>),
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(0x2c => LCR_H: WriteOnly<u32, LCR_H::Register>),
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(0x30 => CR: WriteOnly<u32, CR::Register>),
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(0x34 => _reserved3),
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(0x44 => ICR: WriteOnly<u32, ICR::Register>),
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(0x48 => @END),
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}
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}
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/// Abstraction for the associated MMIO registers.
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type Registers = MMIODerefWrapper<RegisterBlock>;
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#[derive(PartialEq)]
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enum BlockingMode {
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Blocking,
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NonBlocking,
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}
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//--------------------------------------------------------------------------------------------------
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// Public Definitions
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//--------------------------------------------------------------------------------------------------
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pub struct PL011UartInner {
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registers: Registers,
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chars_written: usize,
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chars_read: usize,
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}
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// Export the inner struct so that BSPs can use it for the panic handler.
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pub use PL011UartInner as PanicUart;
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/// Representation of the UART.
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pub struct PL011Uart {
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inner: NullLock<PL011UartInner>,
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}
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//--------------------------------------------------------------------------------------------------
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// Public Code
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//--------------------------------------------------------------------------------------------------
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impl PL011UartInner {
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/// Create an instance.
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///
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/// # Safety
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///
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/// - The user must ensure to provide a correct MMIO start address.
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pub const unsafe fn new(mmio_start_addr: usize) -> Self {
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Self {
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registers: Registers::new(mmio_start_addr),
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chars_written: 0,
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chars_read: 0,
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}
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}
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/// Set up baud rate and characteristics.
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///
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/// This results in 8N1 and 921_600 baud.
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///
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/// The calculation for the BRD is (we set the clock to 48 MHz in config.txt):
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/// `(48_000_000 / 16) / 921_600 = 3.2552083`.
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///
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/// This means the integer part is `3` and goes into the `IBRD`.
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/// The fractional part is `0.2552083`.
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///
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/// `FBRD` calculation according to the PL011 Technical Reference Manual:
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/// `INTEGER((0.2552083 * 64) + 0.5) = 16`.
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///
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/// Therefore, the generated baud rate divider is: `3 + 16/64 = 3.25`. Which results in a
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/// genrated baud rate of `48_000_000 / (16 * 3.25) = 923_077`.
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///
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/// Error = `((923_077 - 921_600) / 921_600) * 100 = 0.16%`.
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pub fn init(&mut self) {
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// Execution can arrive here while there are still characters queued in the TX FIFO and
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// actively being sent out by the UART hardware. If the UART is turned off in this case,
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// those queued characters would be lost.
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//
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// For example, this can happen during runtime on a call to panic!(), because panic!()
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// initializes its own UART instance and calls init().
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//
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// Hence, flush first to ensure all pending characters are transmitted.
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self.flush();
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// Turn the UART off temporarily.
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self.registers.CR.set(0);
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// Clear all pending interrupts.
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self.registers.ICR.write(ICR::ALL::CLEAR);
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// From the PL011 Technical Reference Manual:
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//
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// The LCR_H, IBRD, and FBRD registers form the single 30-bit wide LCR Register that is
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// updated on a single write strobe generated by a LCR_H write. So, to internally update the
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// contents of IBRD or FBRD, a LCR_H write must always be performed at the end.
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//
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// Set the baud rate, 8N1 and FIFO enabled.
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self.registers.IBRD.write(IBRD::BAUD_DIVINT.val(3));
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self.registers.FBRD.write(FBRD::BAUD_DIVFRAC.val(16));
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self.registers
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.LCR_H
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.write(LCR_H::WLEN::EightBit + LCR_H::FEN::FifosEnabled);
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// Turn the UART on.
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self.registers
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.CR
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.write(CR::UARTEN::Enabled + CR::TXE::Enabled + CR::RXE::Enabled);
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}
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/// Send a character.
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fn write_char(&mut self, c: char) {
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// Spin while TX FIFO full is set, waiting for an empty slot.
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while self.registers.FR.matches_all(FR::TXFF::SET) {
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cpu::nop();
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}
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// Write the character to the buffer.
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self.registers.DR.set(c as u32);
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self.chars_written += 1;
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}
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/// Block execution until the last buffered character has been physically put on the TX wire.
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fn flush(&self) {
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// Spin until the busy bit is cleared.
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while self.registers.FR.matches_all(FR::BUSY::SET) {
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4 years ago
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cpu::nop();
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}
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}
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/// Retrieve a character.
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fn read_char_converting(&mut self, blocking_mode: BlockingMode) -> Option<char> {
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// If RX FIFO is empty,
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if self.registers.FR.matches_all(FR::RXFE::SET) {
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// immediately return in non-blocking mode.
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if blocking_mode == BlockingMode::NonBlocking {
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return None;
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}
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// Otherwise, wait until a char was received.
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while self.registers.FR.matches_all(FR::RXFE::SET) {
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cpu::nop();
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}
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}
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// Read one character.
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let mut ret = self.registers.DR.get() as u8 as char;
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// Convert carrige return to newline.
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if ret == '\r' {
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ret = '\n'
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}
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// Update statistics.
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self.chars_read += 1;
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Some(ret)
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}
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5 years ago
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}
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/// Implementing `core::fmt::Write` enables usage of the `format_args!` macros, which in turn are
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/// used to implement the `kernel`'s `print!` and `println!` macros. By implementing `write_str()`,
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/// we get `write_fmt()` automatically.
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///
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/// The function takes an `&mut self`, so it must be implemented for the inner struct.
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///
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/// See [`src/print.rs`].
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///
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/// [`src/print.rs`]: ../../print/index.html
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impl fmt::Write for PL011UartInner {
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fn write_str(&mut self, s: &str) -> fmt::Result {
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for c in s.chars() {
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self.write_char(c);
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}
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Ok(())
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}
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}
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impl PL011Uart {
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4 years ago
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/// Create an instance.
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///
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5 years ago
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/// # Safety
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///
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4 years ago
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/// - The user must ensure to provide a correct MMIO start address.
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pub const unsafe fn new(mmio_start_addr: usize) -> Self {
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Self {
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inner: NullLock::new(PL011UartInner::new(mmio_start_addr)),
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}
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}
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}
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5 years ago
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//------------------------------------------------------------------------------
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// OS Interface Code
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//------------------------------------------------------------------------------
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use synchronization::interface::Mutex;
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5 years ago
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5 years ago
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impl driver::interface::DeviceDriver for PL011Uart {
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fn compatible(&self) -> &'static str {
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5 years ago
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"BCM PL011 UART"
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}
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4 years ago
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unsafe fn init(&self) -> Result<(), &'static str> {
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4 years ago
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self.inner.lock(|inner| inner.init());
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5 years ago
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Ok(())
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}
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}
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5 years ago
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impl console::interface::Write for PL011Uart {
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5 years ago
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/// Passthrough of `args` to the `core::fmt::Write` implementation, but guarded by a Mutex to
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/// serialize access.
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fn write_char(&self, c: char) {
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self.inner.lock(|inner| inner.write_char(c));
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}
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fn write_fmt(&self, args: core::fmt::Arguments) -> fmt::Result {
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// Fully qualified syntax for the call to `core::fmt::Write::write:fmt()` to increase
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// readability.
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self.inner.lock(|inner| fmt::Write::write_fmt(inner, args))
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}
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4 years ago
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fn flush(&self) {
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// Spin until TX FIFO empty is set.
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self.inner.lock(|inner| inner.flush());
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}
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5 years ago
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}
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5 years ago
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impl console::interface::Read for PL011Uart {
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5 years ago
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fn read_char(&self) -> char {
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4 years ago
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self.inner
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.lock(|inner| inner.read_char_converting(BlockingMode::Blocking).unwrap())
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}
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5 years ago
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4 years ago
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fn clear_rx(&self) {
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// Read from the RX FIFO until it is indicating empty.
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while self
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.inner
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.lock(|inner| inner.read_char_converting(BlockingMode::NonBlocking))
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.is_some()
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{}
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5 years ago
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}
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}
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5 years ago
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impl console::interface::Statistics for PL011Uart {
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5 years ago
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fn chars_written(&self) -> usize {
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4 years ago
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self.inner.lock(|inner| inner.chars_written)
|
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5 years ago
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}
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||
5 years ago
|
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fn chars_read(&self) -> usize {
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||
4 years ago
|
self.inner.lock(|inner| inner.chars_read)
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||
5 years ago
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}
|
||
5 years ago
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}
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