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// SPDX-License-Identifier: MIT OR Apache-2.0
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//
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// Copyright (c) 2018-2020 Andre Richter <andre.o.richter@gmail.com>
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//! PL011 UART driver.
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use crate::{
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bsp::device_driver::common::MMIODerefWrapper, console, cpu, driver, synchronization,
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synchronization::NullLock,
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};
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use core::fmt;
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use register::{mmio::*, register_bitfields, register_structs};
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//--------------------------------------------------------------------------------------------------
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// Private Definitions
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//--------------------------------------------------------------------------------------------------
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// PL011 UART registers.
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//
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// Descriptions taken from
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// https://github.com/raspberrypi/documentation/files/1888662/BCM2837-ARM-Peripherals.-.Revised.-.V2-1.pdf
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register_bitfields! {
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u32,
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/// Flag Register
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FR [
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/// Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
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/// Line Control Register, UARTLCR_ LCRH.
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///
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/// If the FIFO is disabled, this bit is set when the transmit holding register is empty. If
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/// the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does
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/// not indicate if there is data in the transmit shift register.
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TXFE OFFSET(7) NUMBITS(1) [],
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/// Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the
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/// UARTLCR_ LCRH Register.
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///
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/// If the FIFO is disabled, this bit is set when the transmit holding register is full. If
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/// the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
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TXFF OFFSET(5) NUMBITS(1) [],
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/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
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/// UARTLCR_H Register.
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///
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/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
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/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
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RXFE OFFSET(4) NUMBITS(1) []
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],
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/// Integer Baud rate divisor
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IBRD [
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/// Integer Baud rate divisor
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IBRD OFFSET(0) NUMBITS(16) []
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],
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/// Fractional Baud rate divisor
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FBRD [
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/// Fractional Baud rate divisor
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FBRD OFFSET(0) NUMBITS(6) []
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],
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/// Line Control register
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LCRH [
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/// Word length. These bits indicate the number of data bits transmitted or received in a
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/// frame.
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WLEN OFFSET(5) NUMBITS(2) [
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FiveBit = 0b00,
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SixBit = 0b01,
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SevenBit = 0b10,
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EightBit = 0b11
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],
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/// Enable FIFOs:
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///
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/// 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding
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/// registers
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///
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/// 1 = transmit and receive FIFO buffers are enabled (FIFO mode).
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FEN OFFSET(4) NUMBITS(1) [
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FifosDisabled = 0,
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FifosEnabled = 1
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]
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],
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/// Control Register
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CR [
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/// Receive enable. If this bit is set to 1, the receive section of the UART is enabled.
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/// Data reception occurs for UART signals. When the UART is disabled in the middle of
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/// reception, it completes the current character before stopping.
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RXE OFFSET(9) NUMBITS(1) [
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Disabled = 0,
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Enabled = 1
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],
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/// Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled.
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/// Data transmission occurs for UART signals. When the UART is disabled in the middle of
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/// transmission, it completes the current character before stopping.
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TXE OFFSET(8) NUMBITS(1) [
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Disabled = 0,
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Enabled = 1
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],
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/// UART enable
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UARTEN OFFSET(0) NUMBITS(1) [
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/// If the UART is disabled in the middle of transmission or reception, it completes the
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/// current character before stopping.
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Disabled = 0,
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Enabled = 1
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]
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],
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/// Interrupt Clear Register
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ICR [
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/// Meta field for all pending interrupts
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ALL OFFSET(0) NUMBITS(11) []
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]
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}
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register_structs! {
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#[allow(non_snake_case)]
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pub RegisterBlock {
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(0x00 => DR: ReadWrite<u32>),
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(0x04 => _reserved1),
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(0x18 => FR: ReadOnly<u32, FR::Register>),
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(0x1c => _reserved2),
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(0x24 => IBRD: WriteOnly<u32, IBRD::Register>),
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(0x28 => FBRD: WriteOnly<u32, FBRD::Register>),
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(0x2c => LCRH: WriteOnly<u32, LCRH::Register>),
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(0x30 => CR: WriteOnly<u32, CR::Register>),
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(0x34 => _reserved3),
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(0x44 => ICR: WriteOnly<u32, ICR::Register>),
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(0x48 => @END),
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}
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}
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/// Abstraction for the associated MMIO registers.
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type Registers = MMIODerefWrapper<RegisterBlock>;
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//--------------------------------------------------------------------------------------------------
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// Public Definitions
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//--------------------------------------------------------------------------------------------------
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pub struct PL011UartInner {
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registers: Registers,
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chars_written: usize,
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chars_read: usize,
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}
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// Export the inner struct so that BSPs can use it for the panic handler.
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pub use PL011UartInner as PanicUart;
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/// Representation of the UART.
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pub struct PL011Uart {
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inner: NullLock<PL011UartInner>,
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}
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//--------------------------------------------------------------------------------------------------
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// Public Code
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//--------------------------------------------------------------------------------------------------
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impl PL011UartInner {
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/// Create an instance.
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///
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/// # Safety
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///
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/// - The user must ensure to provide the correct `base_addr`.
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pub const unsafe fn new(base_addr: usize) -> Self {
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Self {
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registers: Registers::new(base_addr),
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chars_written: 0,
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chars_read: 0,
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}
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}
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/// Set up baud rate and characteristics.
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///
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/// Results in 8N1 and 230400 baud (if the clk has been previously set to 48 MHz by the
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/// firmware).
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pub fn init(&mut self) {
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// Turn it off temporarily.
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self.registers.CR.set(0);
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self.registers.ICR.write(ICR::ALL::CLEAR);
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self.registers.IBRD.write(IBRD::IBRD.val(13));
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self.registers.FBRD.write(FBRD::FBRD.val(1));
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self.registers
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.LCRH
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.write(LCRH::WLEN::EightBit + LCRH::FEN::FifosEnabled); // 8N1 + Fifo on
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self.registers
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.CR
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.write(CR::UARTEN::Enabled + CR::TXE::Enabled + CR::RXE::Enabled);
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}
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/// Send a character.
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fn write_char(&mut self, c: char) {
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// Spin while TX FIFO full is set, waiting for an empty slot.
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while self.registers.FR.matches_all(FR::TXFF::SET) {
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cpu::nop();
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}
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// Write the character to the buffer.
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self.registers.DR.set(c as u32);
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self.chars_written += 1;
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}
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}
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/// Implementing `core::fmt::Write` enables usage of the `format_args!` macros, which in turn are
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/// used to implement the `kernel`'s `print!` and `println!` macros. By implementing `write_str()`,
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/// we get `write_fmt()` automatically.
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///
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/// The function takes an `&mut self`, so it must be implemented for the inner struct.
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///
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/// See [`src/print.rs`].
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///
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/// [`src/print.rs`]: ../../print/index.html
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impl fmt::Write for PL011UartInner {
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fn write_str(&mut self, s: &str) -> fmt::Result {
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for c in s.chars() {
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self.write_char(c);
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}
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Ok(())
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}
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}
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impl PL011Uart {
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/// # Safety
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///
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/// - The user must ensure to provide the correct `base_addr`.
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pub const unsafe fn new(base_addr: usize) -> Self {
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Self {
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inner: NullLock::new(PL011UartInner::new(base_addr)),
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}
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}
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}
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//------------------------------------------------------------------------------
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// OS Interface Code
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//------------------------------------------------------------------------------
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use synchronization::interface::Mutex;
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impl driver::interface::DeviceDriver for PL011Uart {
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fn compatible(&self) -> &str {
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"BCM PL011 UART"
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}
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fn init(&self) -> Result<(), ()> {
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let mut r = &self.inner;
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r.lock(|inner| inner.init());
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Ok(())
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}
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}
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impl console::interface::Write for PL011Uart {
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/// Passthrough of `args` to the `core::fmt::Write` implementation, but guarded by a Mutex to
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/// serialize access.
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fn write_char(&self, c: char) {
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let mut r = &self.inner;
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r.lock(|inner| inner.write_char(c));
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}
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fn write_fmt(&self, args: core::fmt::Arguments) -> fmt::Result {
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// Fully qualified syntax for the call to `core::fmt::Write::write:fmt()` to increase
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// readability.
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let mut r = &self.inner;
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r.lock(|inner| fmt::Write::write_fmt(inner, args))
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}
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fn flush(&self) {
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// Spin until TX FIFO empty is set.
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let mut r = &self.inner;
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r.lock(|inner| {
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while !inner.registers.FR.matches_all(FR::TXFE::SET) {
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cpu::nop();
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}
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});
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}
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}
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impl console::interface::Read for PL011Uart {
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fn read_char(&self) -> char {
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let mut r = &self.inner;
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r.lock(|inner| {
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// Spin while RX FIFO empty is set.
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while inner.registers.FR.matches_all(FR::RXFE::SET) {
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cpu::nop();
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}
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// Read one character.
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let mut ret = inner.registers.DR.get() as u8 as char;
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// Convert carrige return to newline.
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if ret == '\r' {
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ret = '\n'
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}
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// Update statistics.
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inner.chars_read += 1;
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ret
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})
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}
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fn clear(&self) {
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let mut r = &self.inner;
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r.lock(|inner| {
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// Read from the RX FIFO until it is indicating empty.
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while !inner.registers.FR.matches_all(FR::RXFE::SET) {
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inner.registers.DR.get();
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}
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})
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}
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}
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impl console::interface::Statistics for PL011Uart {
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fn chars_written(&self) -> usize {
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let mut r = &self.inner;
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r.lock(|inner| inner.chars_written)
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}
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fn chars_read(&self) -> usize {
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let mut r = &self.inner;
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r.lock(|inner| inner.chars_read)
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}
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}
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