8 Commits (main)

Author	SHA1	Message	Date
dcpedit	397f584060	Regenerate jlcpcb files	4 months ago
dcpedit	ef1d198c29	Blackpill support	2 years ago
Alex Băluț	4577842121	Update to the new project file format (#47) ... I opened and saved the project and its schematic, PCB, etc. Some got saved with a different file name extension. `kinx-cache.lib` had to been renamed to `kint-cache.lib` otherwise the Schematic editor would complain that the file is missing. Then I removed it as I was told in the IRC channel that after saving the schematic in the new format, the symbols will be embedded and it's no longer needed. When opening the PCB there was a warning: > If the zones on this board are refilled the Copper Edge Clearance > setting will be used (see Board Setup > Design Rules > Constraints). > This may result in different fills from previous KiCad versions which > used the line thicknesses of the board boundary on the Edge Cuts > layer. The File > Board Setup > Design Rules > Constraints > Copper Edge Clearance is 0.05mm. Clicking the board boundary belonging to the Edge Cuts layer reveals a properties dialog with Line Width 0.05mm. Being the same, nothing should change at the next refill. The `.gitignore` file has been updated from its original source.	2 years ago
Michael Stapelberg	2a4d3f6a05	gitignore: all kicad files	4 years ago
Michael Stapelberg	46d353ba12	gitignore: -bak files	4 years ago
Michael Stapelberg	8da0aeff26	update .gitignore	6 years ago
Moritz Augsburger	b5d70719a6	ignore autorouter stats	11 years ago
Moritz Augsburger	d5854c85ab	ignore eagle backup files	11 years ago