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@ -111,6 +111,51 @@ static TrackBits GetRailTrackBitsUniversal(TileIndex t, byte *override)
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}
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}
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/**
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* Masks out track bits when neighbouring tiles are unelectrified.
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*/
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static TrackBits MaskWireBits(TileIndex t, TrackBits tracks)
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{
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if (!IsTileType(t, MP_RAILWAY) || !IsPlainRailTile(t)) return tracks;
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TrackdirBits neighbour_tdb = TRACKDIR_BIT_NONE;
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for (DiagDirection d = DIAGDIR_BEGIN; d < DIAGDIR_END; d++) {
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/* If the neighbor tile is either not electrified or has no tracks that can be reached
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* from this tile, mark all trackdirs that can be reached from the neighbour tile
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* as needing no catenary. */
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RailType rt = GetTileRailType(TileAddByDiagDir(t, d));
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if (rt == INVALID_RAILTYPE || !HasCatenary(rt) || (TrackStatusToTrackBits(GetTileTrackStatus(TileAddByDiagDir(t, d), TRANSPORT_RAIL, 0)) & DiagdirReachesTracks(d)) == TRACK_BIT_NONE) {
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neighbour_tdb |= DiagdirReachesTrackdirs(ReverseDiagDir(d));
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}
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}
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/* If the tracks from either a diagonal crossing or don't overlap, both
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* trackdirs have to be marked to mask the corresponding track bit. Else
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* one marked trackdir is enough the mask the track bit. */
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TrackBits mask;
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if (tracks == TRACK_BIT_CROSS || !TracksOverlap(tracks)) {
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/* If the tracks form either a diagonal crossing or don't overlap, both
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* trackdirs have to be marked to mask the corresponding track bit. */
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mask = ~(TrackBits)((neighbour_tdb & (neighbour_tdb >> 8)) & TRACK_BIT_MASK);
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/* If that results in no masked tracks and it is not a diagonal crossing,
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* require only one marked trackdir to mask. */
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if (tracks != TRACK_BIT_CROSS && (mask & TRACK_BIT_MASK) == TRACK_BIT_MASK) mask = ~TrackdirBitsToTrackBits(neighbour_tdb);
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} else {
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/* Require only one marked trackdir to mask the track. */
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mask = ~TrackdirBitsToTrackBits(neighbour_tdb);
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/* If that results in an empty set, require both trackdirs for diagonal track. */
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if ((tracks & mask) == TRACK_BIT_NONE) {
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if ((neighbour_tdb & TRACKDIR_BIT_X_NE) == 0 || (neighbour_tdb & TRACKDIR_BIT_X_SW) == 0) mask |= TRACK_BIT_X;
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if ((neighbour_tdb & TRACKDIR_BIT_Y_NW) == 0 || (neighbour_tdb & TRACKDIR_BIT_Y_SE) == 0) mask |= TRACK_BIT_Y;
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/* If that still is not enough, require both trackdirs for any track. */
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if ((tracks & mask) == TRACK_BIT_NONE) mask = ~(TrackBits)((neighbour_tdb & (neighbour_tdb >> 8)) & TRACK_BIT_MASK);
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}
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}
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/* Mask the tracks only if at least one track bit would remain. */
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return (tracks & mask) != TRACK_BIT_NONE ? tracks & mask : tracks;
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}
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/**
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* Get the base wire sprite to use.
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*/
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@ -212,6 +257,7 @@ static void DrawCatenaryRailway(const TileInfo *ti)
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* the track configuration of 2 adjacent tiles. trackconfig[0] stores the
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* current tile (home tile) while [1] holds the neighbour */
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TrackBits trackconfig[TS_END];
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TrackBits wireconfig[TS_END];
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bool isflat[TS_END];
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/* Note that ti->tileh has already been adjusted for Foundations */
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Slope tileh[TS_END] = { ti->tileh, SLOPE_FLAT };
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@ -233,6 +279,7 @@ static void DrawCatenaryRailway(const TileInfo *ti)
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* because that one is drawn on the bridge. Exception is for length 0 bridges
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* which have no middle tiles */
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trackconfig[TS_HOME] = GetRailTrackBitsUniversal(ti->tile, &OverridePCP);
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wireconfig[TS_HOME] = MaskWireBits(ti->tile, trackconfig[TS_HOME]);
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/* If a track bit is present that is not in the main direction, the track is level */
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isflat[TS_HOME] = ((trackconfig[TS_HOME] & (TRACK_BIT_HORZ | TRACK_BIT_VERT)) != 0);
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@ -240,7 +287,7 @@ static void DrawCatenaryRailway(const TileInfo *ti)
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SpriteID pylon_base = GetPylonBase(ti->tile);
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for (DiagDirection i = DIAGDIR_NE; i < DIAGDIR_END; i++) {
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for (DiagDirection i = DIAGDIR_BEGIN; i < DIAGDIR_END; i++) {
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TileIndex neighbour = ti->tile + TileOffsByDiagDir(i);
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Foundation foundation = FOUNDATION_NONE;
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byte elevation = GetPCPElevation(ti->tile, i);
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@ -249,11 +296,12 @@ static void DrawCatenaryRailway(const TileInfo *ti)
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* existing foundataions, so we do have to do that manually later on.*/
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tileh[TS_NEIGHBOUR] = GetTileSlope(neighbour, NULL);
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trackconfig[TS_NEIGHBOUR] = GetRailTrackBitsUniversal(neighbour, NULL);
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if (IsTunnelTile(neighbour) && i != GetTunnelBridgeDirection(neighbour)) trackconfig[TS_NEIGHBOUR] = TRACK_BIT_NONE;
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wireconfig[TS_NEIGHBOUR] = MaskWireBits(neighbour, trackconfig[TS_NEIGHBOUR]);
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if (IsTunnelTile(neighbour) && i != GetTunnelBridgeDirection(neighbour)) wireconfig[TS_NEIGHBOUR] = trackconfig[TS_NEIGHBOUR] = TRACK_BIT_NONE;
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/* If the neighboured tile does not smoothly connect to the current tile (because of a foundation),
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* we have to draw all pillars on the current tile. */
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if (elevation != GetPCPElevation(neighbour, ReverseDiagDir(i))) trackconfig[TS_NEIGHBOUR] = TRACK_BIT_NONE;
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if (elevation != GetPCPElevation(neighbour, ReverseDiagDir(i))) wireconfig[TS_NEIGHBOUR] = trackconfig[TS_NEIGHBOUR] = TRACK_BIT_NONE;
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isflat[TS_NEIGHBOUR] = ((trackconfig[TS_NEIGHBOUR] & (TRACK_BIT_HORZ | TRACK_BIT_VERT)) != 0);
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@ -272,12 +320,15 @@ static void DrawCatenaryRailway(const TileInfo *ti)
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/* We check whether the track in question (k) is present in the tile
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* (TrackSourceTile) */
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if (HasBit(trackconfig[TrackSourceTile[i][k]], TracksAtPCP[i][k])) {
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DiagDirection PCPpos = i;
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if (HasBit(wireconfig[TrackSourceTile[i][k]], TracksAtPCP[i][k])) {
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/* track found, if track is in the neighbour tile, adjust the number
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* of the PCP for preferred/allowed determination*/
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DiagDirection PCPpos = (TrackSourceTile[i][k] == TS_HOME) ? i : ReverseDiagDir(i);
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PCPpos = (TrackSourceTile[i][k] == TS_HOME) ? i : ReverseDiagDir(i);
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SetBit(PCPstatus, i); // This PCP is in use
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}
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if (HasBit(trackconfig[TrackSourceTile[i][k]], TracksAtPCP[i][k])) {
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PPPpreferred[i] &= PreferredPPPofTrackAtPCP[TracksAtPCP[i][k]][PCPpos];
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PPPallowed[i] &= ~DisallowedPPPofTrackAtPCP[TracksAtPCP[i][k]][PCPpos];
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}
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@ -342,7 +393,7 @@ static void DrawCatenaryRailway(const TileInfo *ti)
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/* Don't build the pylon if it would be outside the tile */
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if (!HasBit(OwnedPPPonPCP[i], temp)) {
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/* We have a neighour that will draw it, bail out */
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if (trackconfig[TS_NEIGHBOUR] != 0) break;
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if (trackconfig[TS_NEIGHBOUR] != TRACK_BIT_NONE) break;
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continue; /* No neighbour, go looking for a better position */
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}
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@ -369,7 +420,7 @@ static void DrawCatenaryRailway(const TileInfo *ti)
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/* Drawing of pylons is finished, now draw the wires */
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for (Track t = TRACK_BEGIN; t < TRACK_END; t++) {
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if (HasBit(trackconfig[TS_HOME], t)) {
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if (HasBit(wireconfig[TS_HOME], t)) {
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byte PCPconfig = HasBit(PCPstatus, PCPpositions[t][0]) +
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(HasBit(PCPstatus, PCPpositions[t][1]) << 1);
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