Progsig: Fix some benign compiler warnings and whitespace issues.

pull/3/head
Jonathan G Rennison 9 years ago
parent 9283ae38df
commit 0693d3678a

@ -355,6 +355,7 @@ public:
{
uint64 p1 = 0;
while(true) {
if(si == NULL) break;
switch(si->Opcode()) {
case PSO_SET_SIGNAL: {
SB(p1, 0, 3, this->track);
@ -365,6 +366,7 @@ public:
this->RebuildInstructionList();
si = ((SignalSet*)si)->next;
} break;
case PSO_IF: {
SB(p1, 0, 3, this->track);
SB(p1, 3, 16, next);
@ -393,11 +395,15 @@ public:
si = ((SignalIf*)si)->after;
} break;
case PSO_LAST:
case PSO_IF_ELSE:
case PSO_IF_ENDIF:
return;
default:
NOT_REACHED();
}
if(si == NULL) break;
if(si->Opcode() == PSO_LAST) break;
if(si->Opcode() == PSO_IF_ELSE) break;
if(si->Opcode() == PSO_IF_ENDIF) break;
}
}

@ -23,30 +23,30 @@ typedef std::vector<byte> Buffer;
static void WriteVLI(Buffer &b, uint i)
{
uint lsmask = 0x7F;
uint msmask = ~0x7F;
while(i & msmask) {
byte part = (i & lsmask) | 0x80;
b.push_back(part);
i >>= 7;
}
b.push_back((byte) i);
uint lsmask = 0x7F;
uint msmask = ~0x7F;
while(i & msmask) {
byte part = (i & lsmask) | 0x80;
b.push_back(part);
i >>= 7;
}
b.push_back((byte) i);
}
static uint ReadVLI()
{
uint shift = 0;
uint val = 0;
byte b;
b = SlReadByte();
while(b & 0x80) {
val |= uint(b & 0x7F) << shift;
shift += 7;
b = SlReadByte();
}
val |= uint(b) << shift;
return val;
uint shift = 0;
uint val = 0;
byte b;
b = SlReadByte();
while(b & 0x80) {
val |= uint(b & 0x7F) << shift;
shift += 7;
b = SlReadByte();
}
val |= uint(b) << shift;
return val;
}
static void WriteCondition(Buffer &b, SignalCondition *c)
@ -59,13 +59,13 @@ static void WriteCondition(Buffer &b, SignalCondition *c)
WriteVLI(b, vc->comparator);
WriteVLI(b, vc->value);
} break;
case PSC_SIGNAL_STATE: {
SignalStateCondition *sc = static_cast<SignalStateCondition*>(c);
WriteVLI(b, sc->sig_tile);
WriteVLI(b, sc->sig_track);
} break;
default:
break;
}
@ -83,13 +83,13 @@ static SignalCondition *ReadCondition(SignalReference this_sig)
c->value = ReadVLI();
return c;
}
case PSC_SIGNAL_STATE: {
TileIndex ti = (TileIndex) ReadVLI();
Trackdir td = (Trackdir) ReadVLI();
return new SignalStateCondition(this_sig, ti, td);
}
default:
return new SignalSimpleCondition(code);
}
@ -111,17 +111,16 @@ static void Save_SPRG()
if(i == e) break;
}
}
// OK, we can now write out our programs
Buffer b;
WriteVLI(b, _signal_programs.size());
for(ProgramList::iterator i = _signal_programs.begin(), e = _signal_programs.end();
i != e; ++i) {
SignalReference ref = i->first;
SignalProgram *prog = i->second;
prog->DebugPrintProgram();
WriteVLI(b, prog->tile);
WriteVLI(b, prog->track);
WriteVLI(b, prog->instructions.Length());
@ -137,44 +136,45 @@ static void Save_SPRG()
WriteVLI(b, s->next->Id());
break;
}
case PSO_LAST: break;
case PSO_IF: {
SignalIf *i = static_cast<SignalIf*>(insn);
WriteCondition(b, i->condition);
WriteVLI(b, i->if_true->Id());
WriteVLI(b, i->if_true->Id());
WriteVLI(b, i->if_false->Id());
WriteVLI(b, i->after->Id());
break;
}
case PSO_IF_ELSE:
case PSO_IF_ENDIF: {
SignalIf::PseudoInstruction *p = static_cast<SignalIf::PseudoInstruction*>(insn);
WriteVLI(b, p->block->Id());
break;
}
case PSO_SET_SIGNAL: {
SignalSet *s = static_cast<SignalSet*>(insn);
WriteVLI(b, s->next->Id());
WriteVLI(b, s->to_state ? 1 : 0);
break;
}
default: NOT_REACHED();
}
}
}
uint size = b.size();
SlSetLength(size);
for(uint i = 0; i < size; i++)
for(uint i = 0; i < size; i++) {
SlWriteByte(b[i]); // TODO Gotta be a better way
}
}
// We don't know the pointer values that need to be stored in various
// We don't know the pointer values that need to be stored in various
// instruction fields at load time, so we need to instead store the IDs and
// then fix them up once all of the instructions have been loaded.
//
@ -185,7 +185,7 @@ struct Fixup {
Fixup(SignalInstruction **p, SignalOpcode type)
: type(type), ptr(p)
{}
SignalOpcode type;
SignalInstruction **ptr;
};
@ -205,9 +205,9 @@ static void DoFixups(FixupList &l, InstructionList &il)
uint id = reinterpret_cast<size_t>(*i->ptr);
if(id >= il.Length())
NOT_REACHED();
*i->ptr = il[id];
if(i->type != PSO_INVALID && (*i->ptr)->Opcode() != i->type) {
DEBUG(sl, 0, "Expected Id %d to be %d, but was in fact %d", id, i->type, (*i->ptr)->Opcode());
NOT_REACHED();
@ -224,10 +224,10 @@ static void Load_SPRG()
Track track = (Track) ReadVLI();
uint instructions = ReadVLI();
SignalReference ref(tile, track);
SignalProgram *sp = new SignalProgram(tile, track, true);
_signal_programs[ref] = sp;
for(uint j = 0; j < instructions; j++) {
SignalOpcode op = (SignalOpcode) ReadVLI();
switch(op) {
@ -237,24 +237,24 @@ static void Load_SPRG()
MakeFixup(l, sp->first_instruction->next, ReadVLI());
break;
}
case PSO_LAST: {
sp->last_instruction = new SignalSpecial(sp, PSO_LAST);
sp->last_instruction->next = NULL;
MakeFixup(l, sp->last_instruction->GetPrevHandle(), ReadVLI());
break;
}
case PSO_IF: {
SignalIf *i = new SignalIf(sp, true);
MakeFixup(l, i->GetPrevHandle(), ReadVLI());
i->condition = ReadCondition(ref);
MakeFixup(l, i->if_true, ReadVLI());
MakeFixup(l, i->if_false, ReadVLI());
MakeFixup(l, i->after, ReadVLI());
MakeFixup(l, i->if_true, ReadVLI());
MakeFixup(l, i->if_false, ReadVLI());
MakeFixup(l, i->after, ReadVLI());
break;
}
case PSO_IF_ELSE:
case PSO_IF_ENDIF: {
SignalIf::PseudoInstruction *p = new SignalIf::PseudoInstruction(sp, op);
@ -262,7 +262,7 @@ static void Load_SPRG()
MakeFixup(l, p->block, ReadVLI(), PSO_IF);
break;
}
case PSO_SET_SIGNAL: {
SignalSet *s = new SignalSet(sp);
MakeFixup(l, s->GetPrevHandle(), ReadVLI());
@ -271,11 +271,11 @@ static void Load_SPRG()
if(s->to_state > SIGNAL_STATE_MAX) NOT_REACHED();
break;
}
default: NOT_REACHED();
}
}
DoFixups(l, sp->instructions);
sp->DebugPrintProgram();
}

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